LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 251

• Manufacturer Part Number: LPC47S457-NC
• Description: Advanced I/O with X-Bus Interface
• Manufacturer: SMSC [SMSC Corporation]

than the Enable Pulse Width of the nXRD or nXWR Pulse Width Selection (i.e., Case D: 540nsec-40nsec=500nsec
minimum LCDCS Pulse Width)
Note : These min/max values satisfy X-Bus read timing and the supported LCD controllers.
Note 1 : Total minimum cycle time for LCDCS between latches is 1000ns. The LCDCS latches the data when it
transitions from a high to a low level. This should be easily satisfied since the SMBus operates in the micro second
range.
Note 2 : For LCD controllers, A0 is the Read/nWrite control bit and A1 is the Data/Control bit. These two bits are the
LSB in the command byte.
Note 3 : The SMBus needs to wait a minimum of 110 μ sec before it is ready to accept the Data being read. The X-Bus
can complete this transaction on the order of 1 μ sec. To prevent the SMBus from holding the X-Bus for an excessive
amount of time, the X-Bus should be allowed to complete its transaction, storing the data in a register until the SMBus
is ready to take the data. This way the LPC Bus can regain access to the X-Bus. With this implementation, CS1
should go active as soon as the command byte is received, it is determined whether the cycle is a read or write cycle
and the SMBus arbitrates rights to the X-Bus.
Note 4 : The default for the Read/Write Enable Pulse Width is 540ns.
Note 5 : The LCDCS signal will be generated a minimum of 40nsec after nXRD or nXWR transitions to a low state
(i.e., LCDCS = nXWR + nXRD with a delay of 40nsec). The Pulse Width of the LCDCS signal will be 40nsec less
than the Enable Pulse Width of the nXRD or nXWR Pulse Width Selection (i.e., Case D: 540nsec-40nsec=500nsec
minimum LCDCS Pulse Width)
SMSC LPC47S45x
XAD0 - XAD7
nCS[0, 2, 3]
SMB Data
SYMBOL
A[0:3]
LCDCS
nXRd
t1
t2
t3
t4
t5
t6
-
-
CS1
FIGURE 43 − SMBUS TO X-BUS READ CYCLE TIMING FOR LCD AND I/O CYCLES
Command Code
SMB frequency
SMB Bit Rate
Address Setup Time
Address Hold Time
Enable Pulse Width
(See Note 4)
Data Valid to nXRd invalid
Data Hold Time
LCD Address Setup Time
(See Note 5)
Address Received
PARAMETER
A
DATASHEET
S
Slave Address/Rd A
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t
1
t
6
Address
t
3
t
valid data
A: 180
B: 300
C: 420
D: 540
4
MIN
100
140
10
10
40
30
20
*Note: Timing Diagram is not to scale.
Data Byte
t
t
t
5
2
2
TYP
-
-
-
-
-
-
-
-
A#
C: 455
D: 575
A: 215
B: 335
MAX
100
100
190
190
-
-
P
UNIT
μ sec
S
kHz
Rev. 06-01-06
ns
ns
ns
ns
ns
ns