LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 252

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LPC47S457-NC

Manufacturer Part Number
LPC47S457-NC
Description
Advanced I/O with X-Bus Interface
Manufacturer
SMSC [SMSC Corporation]
Datasheet
Note: For Read Cycles initiated by the SMBus, the X-Bus should be accessed as soon as the address (i.e. chip
select) is received. For Write Cycles initiated by the SMBus, the X-Bus should be accessed as soon as the Data Byte
is received. (i.e. chip select & data). No cycle should begin before it is determined to be a read or a write.
11.10 Timing for Serial IRQ’s
Note 1: t
percentage errors indicated in the “Baud Rate” table in the “Serial Port” section.
SMSC LPC47S45x
NAME
NAME
BR
t1
t2
t1
is 1/Baud Rate. The Baud Rate is programmed through the divisor latch registers. Baud Rates have
PCI_CLK
SER_IRQ
SER_IRQ Setup Time to PCI_CLK Rising
SER_IRQ Hold Time to PCI_CLK Rising
Serial Port Data Bit Time
TXD1, 2
Data
Start
DESCRIPTION
DESCRIPTION
FIGURE 44 − SETUP AND HOLD TIME
FIGURE 45 − SERIAL PORT DATA
DATASHEET
t1
Page 252 of 259
Data (5-8 Bits)
t1
MIN
MIN
t2
7
0
Parity
TYP
TYP
t
BR
1
Stop (1-2 Bits)
MAX
MAX
UNITS
UNITS
nsec
nsec
nsec
Rev. 06-01-06

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