LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 213

• Manufacturer Part Number: LPC47S457-NC
• Description: Advanced I/O with X-Bus Interface
• Manufacturer: SMSC [SMSC Corporation]

SMSC LPC47S45x
CMOS Bank 1 Primary
Base Address
(High Byte)
Default = 0x00
on VCC POR, VTR
POR, PCI RESET, and
Soft Reset
CMOS Bank 1 Primary
Base Address
(Low Byte)
Default = 0x74
on
RESET, and Soft Reset
Default = 0x00
on VTR_POR
Bank 1
Default = 0x00
on VCC POR, VTR
POR, and PCI RESET
Bank 0 Shadow
Register
KRST_GA20
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Bits[6:5] reset on VTR
POR only
VCC
NAME
NAME
POR,
PCI
Table 92 − KYBD, Logical Device 7 [Logical Device Number = 0x07]
Table 91 − RTC, Logical Device 6 [Logical Device Number = 0x06]
REG INDEX
REG INDEX
Read-Only
0xF0
0xF1
0xF0
0x62
0x63
R/W
R/W
R/W
R/W
Bits [3:0] Address bits A[11:8]
Bits [7:4] “0000”
Bit [0]
Bits [7:1] Address bits A[7:1]
Bank 1:
Bit[0] = 1 : Lock CMOS RAM 0-1Fh
Bit[1] = 1 : Lock CMOS RAM 20-3Fh
Bit[2] = 1 : Lock CMOS RAM 40-5Fh
Bit[3] = 1 : Lock CMOS RAM 60-7Fh
Bit[7:4] Reserved, set to “0”
Once set, bit[3:0] can not be cleared by a write; bits[3:0] are
cleared on VCC Power On Reset, VCC Power Off, or upon a
PCI Reset. Once lock bits are set, the Host is locked out of
accessing the locked locations as long as VCC is active. When
VCC goes to 0V, the lock bits are cleared.
Shadow of RTC/CMOS Bank 0 Index register
KRESET and GateA20 Select
Bit[7] Polarity Select for P12
Bit[6] M_ISO. Enables/disables isolation of mouse signals into
8042. Does not affect MDAT signal to mouse wakeup (PME)
logic.
1=block mouse clock and data signals into 8042
0= do not block mouse clock and data signals into 8042
Bit[5] K_ISO. Enables/disables isolation of keyboard signals
into 8042. Does not affect KDAT signal to keyboard wakeup
(PME) logic.
1=block keyboard clock and data signals into 8042
0= do not block keyboard clock and data signals into 8042
Bit[4] MLATCH
(default)
= 0 MINT is the 8042 MINT ANDed with Latched MINT
DATASHEET
= 0 P12 active low (default)
= 1 P12 active high
Page 213 of 259
“0”
DEFINITION
DEFINITION
Rev. 06-01-06
STATE
STATE