TLE6230 INFINEON [Infineon Technologies AG], TLE6230 Datasheet
TLE6230
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TLE6230 Summary of contents
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Smart Octal Low-Side Switch Features • Short Circuit Protection • Overtemperature Protection • Overvoltage Protection • 16 bit Serial Data Input and Diagnos- tic Output (2 bit/ch. acc. SPI protocol) • Direct Parallel Control of Four Chan- nels for PWM ...
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RESET GND VS PRG IN1 IN2 & IN3 & IN4 & SO SPI SI Interface 16 bit SCLK CS V2.1 Detailed Block Diagram VS FAULT Channel 1 & Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 ...
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Pin Description Pin Symbol 1 GND Ground 2 NC not connected 3 NC not connected 4 OUT1 Power Output Channel 1 5 OUT2 Power Output Channel 2 6 IN1 Input Channel 1 7 IN2 Input Channel Supply ...
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Maximum Ratings for T Parameter Supply Voltage Continuous Drain Source Voltage (OUT1...OUT8) Input Voltage, All Inputs and Data Lines Load Dump Protection V Load Dump With Automotive Relay Load Ω =400ms; ...
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Electrical Characteristics Parameter and Conditions V = 4 ° 150 °C ; Reset = (unless otherwise specified) 1. Power Supply, Reset 4 Supply Voltage 5 Supply Current ...
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Electrical Characteristics cont. Parameter and Conditions V = 4 ° 150 °C ; Reset = (unless otherwise specified) 5. Diagnostic Functions Open Load Detection Voltage Output Pull ...
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Functional Description The TLE 6230 octal-low-side power switch which provides a serial peripheral inter- face (SPI) to control the 8 power DMOS switches, as well as diagnostic feedback. The power transistors are protected against short to V ...
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Power Transistor Protection Functions Each of the eight output stages has its own zener clamp, which causes a voltage limitation at the power transistor when solenoid loads are switched off. The outputs are provided with a current limitation set to ...
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SO - Serial Output. Diagnostic data bits are shifted ...
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A definite distinction between open load and short to ground is guaranteed by design. The standard way of obtaining diagnostic information is as follows: Clock in serial information into SI pin and wait approximately 150 µs to allow the outputs ...
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CS SCLK MSB Figure 2: Serial Interface Figure 3: Input Timing Diagram CS 0 SCKH t lead SCLK 0.7 V SCLK t valid SO ...
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80% 20% Figure 5: Power Outputs Timing is valid for resistive load with parallel and serial control. Rising edge of chip select initiates the switching Application Circuits µC e.g. ...
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Typical electrical Characteristics Drain-Source on-resistance DS(ON Typical Drain- Source ON-Resistance 1,5 1,4 1,3 1,2 1,1 1 0,9 0,8 0,7 0,6 0,5 0,4 -50 -25 0 Typical ON Resistance versus ...
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Maximum single clamp Energy 300 250 200 150 100 0,2 Maximum Clamp Energy (single event) versus Peak Current Figure 8 : Channel 1-8 Parallel SPI Configuration 4 P x.1-4 MTSR MRST CLK P x x.1-4 ...
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Package and Ordering Code (all dimensions in mm) P-DSO 36-12 TLE 6230 GP Q67006-A9329 V2.1 Ordering Code Page 15 Data Sheet TLE 6230 GP 26. Aug. 2002 ...
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Published by Infineon Technologies AG, Bereichs Kommunikation St.-Martin-Strasse 76, D-81541 München © Infineon Technologies AG 1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of ...