AN983 ETC [List of Unclassifed Manufacturers], AN983 Datasheet - Page 30

• Manufacturer Part Number: AN983
• Description: PCI/miniPCI-to-Ethernet LAN Controller
• Manufacturer: ETC [List of Unclassifed Manufacturers]

R/W* = before writing the transmit and receive operations should be stopped.
CSR1 (offset = 08h), TDR - Transmit demand register
R/W* = before writing the transmit process should be in the suspended state.
CSR2 (offset = 10h), RDR - Receive demand register
R/W* = before writing the receive process should be in the suspended state.
CSR3 (offset = 18h), RDB - Receive descriptor base address
R/W* = before writing the receive process should be stopped.
CSR4 (offset = 20h), TDB - Transmit descriptor base address
R/W* = before writing the transmit process should be stopped.
CSR5 (offset = 28h), SR - Status register
6 ~ 2
1
0
Bit #
31~ 0
Bit #
31 ~ 0 RPDM
Bit #
31~ 2
1, 0
Bit #
31~ 2
1, 0
Bit #
31~ 26
25~ 23
Rev. 1.8
DSL
BAR
SWR
Name
TPDM
Name
Name
SAR
RBND
Name
SAT
TBND
Name
----
BET
Descriptor Skip Length. Defines the gap between two
descriptions in the units of DW.
Bus arbitration
0: receive higher priority
1: transmit higher priority
Software reset
1: reset all internal hardware, except configuration
registers. This signal will be cleared by AN983B itself after it
completed the reset process.
Descriptions
Transmit poll demand
When written any value in suspended state, trigger
read-tx-descriptor process and check the own-bit, if
own-bit = 1, then start transmit process
Descriptions
Receive poll demand
When written
read-rx-descriptor process and check own-bit, if own-
1, then start move data to buffer from FIFO
Descriptions
Start address of receive descriptor
Must be 00, DW boundary
Descriptions
Start address of transmit descriptor
Must be 00, DW boundary
Descriptions
Reserved
Bus Error Type. This field is valid only when bit 13 of CSR5
(fatal bus error) is set. There is no interrupt generated by
this field.
AN983B
any value in suspended state, trigger the
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PCI/miPCI Fast Ethernet Controller with integrated PHY
bit =
0
0
0
Default Val RW Type
ffffffffh
Default Val RW Type
ffffffffh
Default Val RW Type
xxxxxxx
00
Default Val RW Type
xxxxxx
00
Default Val RW Type
000
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
RO
R/W*
RO
RO
30