AN983 ETC [List of Unclassifed Manufacturers], AN983 Datasheet - Page 31

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AN983

Manufacturer Part Number
AN983
Description
PCI/miniPCI-to-Ethernet LAN Controller
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet

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22~ 20
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Rev. 1.8
TS
RS
NISS
AISS
----
FBE
000: parity error, 001: master abort, 010: target abort
011, 1xx: reserved
Transmit State. Report the current transmission state only,
no interrupt will be generated.
000: stop
001: read descriptor
010: transmitting
011: FIFO fill, read the data from memory and put into FIFO
100: reserved
101: reserved
110: suspended, unavailable transmit descriptor or FIFO
overflow
111: write descriptor
Receive State. Report current receive state only, no
interrupt will be generated.
000: stop
001: read descriptor
010: check this packet and pre-fetch next descriptor
011: wait for receiving data
100: suspended
101: write descriptor
110: flush the current FIFO
111: FIFO drain, move data from receiving FIFO into memory
Normal Interrupt Status Summary. It’s set if any of below
bits of CSR5 asserted. (Combines with bit 16 of ACSR5)
Abnormal Interrupt Status Summary. It’s set if any of below
bits of CSR5 asserted. (Combines with bit 15 of ACSR5)
Reserved
Fatal Bus Error.
1: while any of parity error, master abort, or target abort is
occurred (see bits 25~23 of CSR5). AN983B will disable all
bus access. The way to recover parity error is by setting
software reset.
bit0, transmit completed interrupt
bit2, transmit descriptor unavailable
bit6, receive descriptor interrupt
bit1, transmit process stopped
bit3, transmit jabber timer time-out
bit5, transmit under-flow
bit7, receive descriptor unavailable
bit8, receive processor stopped
bit9, receive watchdog time-out
bit11, general purpose timer time-out
bit13, fatal bus error
AN983B
www.admtek.com.tw
ADMtek Inc.
PCI/miPCI Fast Ethernet Controller with integrated PHY
000
000
0
0
0
RO
RO
RO/LH*
RO/LH*
RO/LH*
31

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