AN983 ETC [List of Unclassifed Manufacturers], AN983 Datasheet - Page 53

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AN983

Manufacturer Part Number
AN983
Description
PCI/miniPCI-to-Ethernet LAN Controller
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet

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9
8
7
6
5
4
3
2
1
0
RDES1
Bit #
31~26
25
24
23~22
21~11
10~ 0
RDES2
Bit #
31~0
RDES3
Bit #
31~0
7.4.2. TRANSMIT DESCRIPTOR
7 . 4 . 2 . 1 . T r a n s m i t D e s c r i p t o r T a b l e
Rev. 1.8
FS
LS
TL
CS
FT
RW
Reserved Default = 0
DB
CE
OF
Name
---
RER
RCH
---
RBS2
RBS1
Name
RBA1
Name
RBA2
31
First descriptor.
Last descriptor.
Too long packet (packet length > 1518 bytes). This bit is valid only in last descriptor
Late collision. Set when collision is active after 64 bytes. This bit is valid only in last
descriptor
Frame type. This bit is valid only in last descriptor.
1: Ethernet type
0: 802.3 type
Receive watchdog (refer to CSR15, bit 4). This bit is valid only in last descriptor.
Dribble bit. This bit is valid only in last descriptorEC
Packet length is not integer multiple of 8-bit.
CRC error. This bit is valid only in last descriptor
Overflow. This bit is valid only in last descriptor
Descriptions
Reserved
Receive end of ring
Indicates this descriptor is last, return to base address of descriptor
Second address chain
Use for chain structure. Indicates the buffer2 address is the next descriptor address.
Ring mode takes precedence over chained mode
Reserved
Buffer 2 size (DW boundary)
Buffer 1 size (DW boundary)
Descriptions
Receive Buffer Address 1. This buffer address should be double word aligned.
Descriptions
Receive Buffer Address 2. This buffer address should be double word aligned.
AN983B
www.admtek.com.tw
ADMtek Inc.
PCI/miPCI Fast Ethernet Controller with integrated PHY
53
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