AN983 ETC [List of Unclassifed Manufacturers], AN983 Datasheet - Page 39

• Manufacturer Part Number: AN983
• Description: PCI/miniPCI-to-Ethernet LAN Controller
• Manufacturer: ETC [List of Unclassifed Manufacturers]

CSR16 (offset = 80h), ACSR5 - Assistant CSR5 (Status register 2)
4
3
2
1
0
Bit #
31
30
29
28
27
26
25~17
16
Rev. 1.8
RWD
---
JCLK
NJ
JBD
Name
TEIS
REIS
LCS
TDIS
---
PFR
---
ANISS
watchdog timer from last carrier deserted.
0: 24 bit-time
1: 48 bit-time
Receive Watchdog Disable
0: If the receiving packet
bytes, the watchdog timer will be expired.
1: disable the receive watchdog.
Reserved
Jabber clock
0: cut off transmission after 2.6 ms (100Mbps) or 26 ms
(10Mbps).
1: cut off transmission after 2560 byte-time.
Non-Jabber
0: if jabber expired, re-enable transmit f
42 ms (100Mbps) or 420ms (10Mbps)
1: immediately re-enable the transmit function after
jabber expired
Jabber disable
1: disable transmit jabber function
Descriptions
Transmit Early Interrupt status
Transmit early interrupt status is set to 1 when Transmit
early interrupt function is enabled (set bit 31 of CSR17 = 1)
and the transmitted packet is moved completed from
descriptors to TX-FIFO buffer. This bit is cleared by written
with 1.
Receive Early Interrupt Status.
Receive early interrupt status is set to 1 when Receive early
interrupt function is enabled (set bit 30 of CSR17 = 1) and
the received packet is fill up its first receive descriptor. This
bit is cleared by written with 1.
Status of Link status change
Transmit Deferred Interrupt Status.
Reserved
PAUSE Frame Received Interrupt Status
1: indicates a PAUSE frame received when the PAUSE
function is enabled.
Reserved
Added normal interrupt status summary.
1: any of the added normal interrupts happened.
AN983B
www.admtek.com.tw
ADMtek Inc.
‘s length is longer than 2560
PCI/miPCI Fast Ethernet Controller with integrated PHY
unction after
0
0
0
0
Default Val
0
0
0
0
0
0
R/W
R/W
R/W
R/W
RW
Type
RO/LH*
RO/LH*
RO/LH*
RO/LH*
RO/LH*
RO/LH*
39