AN983 ETC [List of Unclassifed Manufacturers], AN983 Datasheet - Page 41

• Manufacturer Part Number: AN983
• Description: PCI/miniPCI-to-Ethernet LAN Controller
• Manufacturer: ETC [List of Unclassifed Manufacturers]

25
24
23
22, 21
20
19
18
17
16~8
7
Rev. 1.8
PWRS_clr 1: PCI_reset rising will automatically reset CR49/ PWRS[1:0]
Pmes_stic
ky
4_3LED
RFS
CRD
PM
APM
LWS
----
D3_APM
to 00h.
1: pmez sticky: While pmez signal is asserted by wake up
event, it cannot be auto de-asserted. The software should
clear CR49<15> PMES bit to de-assert the pmez signal.
0: pmez auto de-asserted: While pmez signal is asserted by
wake up event, it will be de-asserted by power up
automatically.
If this bit is reset, 3 LED mode is selected, the LEDs
definition is:
100/10 speed
Link/Activity
Full Duplex/Collision
If this bit is set, 4 LED mode is selected, the LEDs definition
is:
100 Link
10 Link
Activity
Full Duplex/Collision
Receive FIFO size control
11: 1K
10: 2K
01,00: reserved
Clock Run (clk-run pin) disable
1: disables the function of clock run supports to PCI.
Power Management, enables the AN983B whether to activate
the Power Management abilities. When this bit is set into “0”
the AN983B will set the Cap_Ptr register to zero, indicating
no PCI compliant power management capabilities.
The value of this bit will be mapped to NC-bit 20 of CR1.
In PCI Power Management mode, the Wake-up events include
“Wake-up Frame Received”, “Magic Packet Received” and
“Link Status Changed” depends on the CSR13 settings
APM mode, this bit is effective when PM (csr18 [19]) =1
1: Magic Packet wake-up event default enable
0: Magic Packet wake-up event default disable
Should be 0
Reserved
D3_cold APM_mode_en for PC99 certification
It doesn’t matter the status of PEM_EN, the pmez signal can
be asserted by programming this bit
1: Assert pmez signal
AN983B
www.admtek.com.tw
ADMtek Inc.
PCI/miPCI Fast Ethernet Controller with integrated PHY
0 from
EERROM
0
From EEPROM
0
From EEPROM
10
From
EEPROM
0
From EEPROM
1
From EEPROM
1
From EEPROM
0
From EEPROM
0
R/W
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
41