PEF20525 INFINEON [Infineon Technologies AG], PEF20525 Datasheet - Page 164
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PEF20525
Manufacturer Part Number
PEF20525
Description
2 Channel Serial Optimized Communication Controller for HDLC/PPP
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
1.PEF20525.pdf
(252 pages)
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Data Sheet
Register 38
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 39
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit
Bit
TEPCM
7
7
0
TTSA0
Transmit Time Slot Assignment Register 0
TTSA1
Transmit Time Slot Assignment Register 1
6
6
0
read/write
00
Channel A
28
written by CPU;
read and evaluated by SEROCCO-H
read/write
00
Channel A
29
written by CPU;
read and evaluated by SEROCCO-H
H
H
H
H
5
5
0
Channel B
78
Channel B
79
Tx Time Slot Number
H
H
5-164
4
4
0
TTSN(6:0)
3
3
0
Register Description (TTSA0)
Tx Clock Shift
2
2
TCS(2:0)
1
1
PEB 20525
PEF 20525
2000-09-14
0
0
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