PMB2304 INFINEON [Infineon Technologies AG], PMB2304 Datasheet - Page 14

• Manufacturer Part Number: PMB2304
• Description: PLL-FREQUENCY SYNTHESIZER
• Manufacturer: INFINEON [Infineon Technologies AG]

Wireless Components
3.4 General Description
3.5 Programming
3.6 Data acquisition
The circuit consists of a reference-, A- and N-counter, a dual modulus control
logic, a phase detector with charge pump output and a serial control logic. The
setting of the operating mode and the selection of the counter ratios is done
serially at the ports CLK, DA and EN.
The operating modes allow the selection of single or dual operation, asynchro-
nous or synchronous data acquisition, 4 different antibacklash-impulse times, 8
different PD-output current modes, polarity setting of the PD-output signal,
adjustment of the trigger-edge of the MOD-output signal, 2 standby modes and
the control of the multifunction outputs MFO1 and MFO2.
The reference frequency is applied at the RI-input and divided by the R-counter.
It’s maximum value is 100 MHz. The VCO-frequency is applied at the FI-input
and divided by the N- or N/A-counter according to single or dual mode opera-
tion. The maximum value at FI is 220 MHz at single-, and 65 MHz at dual mode
operation.
The phase and frequency sensitive phase detector produces an output signal
with adjustable anti-backlash impulses in order to prevent a dead zone for very
small phase deviations. Phase differences of less than 100 ps can be resolved.
In general the shortest anti-backlash pulse gives the best system performance.
Programming of the IC is done by a serial data control. The contents of the mes-
sage are assigned to the functional units according to the address. Single or
dual mode operation as well as asynchronous or synchronous data acquisition
is set by status 2 and should therefore precede the programming of the
counters.
The PMB 2304R offers the possibility of synchronous data acquisition to avoid
error signals at the phase detector due to non-corresponding dividing factors in
the counters produced by asynchronous loading.
Synchronous programming guarantees control during changes of frequency or
channel. That means that the state of the phase detector or the phase
difference is kept maintained, and in case of “lock in”, the control process starts
with the phase difference “zero”.
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Functional Description
Specification, June 2002
PMB 2304R
preliminary