NAND01G-A STMICROELECTRONICS [STMicroelectronics], NAND01G-A Datasheet - Page 17

• Manufacturer Part Number: NAND01G-A
• Description: 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

BUS OPERATIONS
There are six standard bus operations that control
the memory. Each of these is described in this
section, see
mary.
Command Input
Command Input bus operations are used to give
commands to the memory. Command are accept-
ed when Chip Enable is Low, Command Latch En-
able is High, Address Latch Enable is Low and
Read Enable is High. They are latched on the ris-
ing edge of the Write Enable signal.
Only I/O0 to I/O7 are used to input commands.
See
ings requirements.
Address Input
Address Input bus operations are used to input the
memory address. Three bus cycles are required to
input the addresses for the 128Mb and 256Mb de-
vices and four bus cycles are required to input the
addresses for the 512Mb and 1Gb devices (refer
to Tables
The addresses are accepted when Chip Enable is
Low, Address Latch Enable is High, Command
Latch Enable is Low and Read Enable is High.
They are latched on the rising edge of the Write
Enable signal. Only I/O0 to I/O7 are used to input
addresses.
See
ings requirements.
Data Input
Data Input bus operations are used to input the
data to be programmed.
Table 5. Bus Operations
Note: 1. Only for x16 devices.
Command Input
Bus Operation
Address Input
Figure 23.
Figure 24.
Write Protect
Data Output
2. WP must be V
Data Input
Standby
6
and 7, Address Insertion).
Table 5., Bus
and
and
IH
Table 20.
Table 20.
when issuing a program or erase command.
V
V
V
V
V
E
X
IH
IL
IL
IL
IL
Operations, for a sum-
for details of the tim-
for details of the tim-
V
AL
V
V
V
X
X
IL
IH
IL
IL
V
CL
V
V
V
X
X
IH
IL
IL
IL
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Falling
V
V
V
R
X
X
IH
IH
IH
Rising
Rising
Rising
Data is accepted only when Chip Enable is Low,
Address Latch Enable is Low, Command Latch
Enable is Low and Read Enable is High. The data
is latched on the rising edge of the Write Enable
signal. The data is input sequentially using the
Write Enable signal.
See
tails of the timings requirements.
Data Output
Data Output bus operations are used to read: the
data in the memory array, the Status Register, the
Electronic Signature and the Serial Number.
Data is output when Chip Enable is Low, Write En-
able is High, Address Latch Enable is Low, and
Command Latch Enable is Low.
The data is output sequentially using the Read En-
able signal.
See
ings requirements.
Write Protect
Write Protect bus operations are used to protect
the memory against program or erase operations.
When the Write Protect signal is Low the device
will not accept program or erase operations and so
the contents of the memory array cannot be al-
tered. The Write Protect signal is not latched by
Write Enable to ensure protection even during
power-up.
Standby
When Chip Enable is High the memory enters
Standby mode, the device is deselected, outputs
are disabled and power consumption is reduced.
V
W
X
X
IH
Figure 25.
Figure 26.
WP
X
V
X
X
X
X
(2)
IL
and
and
Data Output
I/O0 - I/O7
Command
Data Input
Table 20.
Address
Table 21.
X
X
and
for details of the tim-
Table 21.
I/O8 - I/O15
Data Output
Data Input
X
X
X
X
for de-
(1)
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