NAND01G-A STMICROELECTRONICS [STMicroelectronics], NAND01G-A Datasheet - Page 26

• Manufacturer Part Number: NAND01G-A
• Description: 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Copy Back Program
The Copy Back Program operation is used to copy
the data stored in one page and reprogram it in an-
other page.
The Copy Back Program operation does not re-
quire external memory and so the operation is
faster and more efficient because the reading and
loading cycles are not required. The operation is
particularly useful when a portion of a block is up-
dated and the rest of the block needs to be copied
to the newly assigned block.
If the Copy Back Program operation fails an error
is signalled in the Status Register. However as the
standard external ECC cannot be used with the
Copy Back operation bit error due to charge loss
cannot be detected. For this reason it is recom-
mended to limit the number of Copy Back opera-
tions on the same data and or to improve the
performance of the ECC.
The Copy Back Program operation requires three
steps:
1. The source page must be read using the Read
Figure 18. Copy Back Operation
26/57
RB
I/O
A command (one bus write cycle to setup the
command and then 4 bus write cycles to input
the source page address). This operation
copies all 264 Words/ 528 Bytes from the page
into the Page Buffer.
Read
Code
00h
Address Inputs
Source
(Read Busy time)
tBLBH1
Copy Back
8Ah
Code
Address Inputs
Target
2. When the device returns to the ready state
3. Then the confirm command is issued to start
After a Copy Back Program operation, a partial-
page program is not allowed in the target page un-
til the block has been erased.
See
operation.
Table 10. Copy Back Program Addresses
Note: 1. DD = Dual Die.
512 Mbit DD
(Program Busy time)
1 Gbit DD
(Ready/Busy High), the second bus write
cycle of the command is given with the 4 bus
cycles to input the target page address. Refer
to
same for the Source and Target pages.
the P/E/R Controller.
Figure 18.
128 Mbit
256 Mbit
512 Mbit
Density
Table 10.
tBLBH2
10h
(1)
(1)
for an example of the Copy Back
for the addresses that must be the
Busy
Same Address for Source and
Read Status Register
70h
Target Pages
A24, A25
A25, A26
A23
A24
A25
SR0
ai07590b