NAND01G-A STMICROELECTRONICS [STMicroelectronics], NAND01G-A Datasheet - Page 56

• Manufacturer Part Number: NAND01G-A
• Description: 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

NAND128-A, NAND256-A, NAND512-A, NAND01G-A
REVISION HISTORY
Table 29. Document Revision History
56/57
06-Jun-2003
07-Aug-2003
27-Oct-2003
03-Dec-2003
13-Apr-2004
28-May-2004
02-Jul-2004
01-Oct-2004
03-Dec-2004
13-Dec-2004
25-Feb-2005
Date
Version
10.0
11.0
3.0
1.0
2.0
4.0
5.0
6.0
7.0
8.0
9.0
First Issue
Design Phase
Engineering Phase
Document promoted from Target Specification to Preliminary Data status.
V
Title of
for NANDXXXR3A devices corrected.
WSOP48 and VFBGA55 packages added, VFBGA63 (9 x 11 x 1mm) removed.
Figure 19., Cache Program
for t
Meaning of t
modified in
References removed from
made to ST Website instead.
Figure
paragraph clarified and
modified. Note 2 to
Note 3 to
operations are valid before a Cache Program operation. I
18., DC Characteristics, 1.8V
Waveform. Small text changes.
TFBGA55 package added (mechanical data to be announced). 512Mb Dual Die
devices added.
Package code changed for TFBGA63 8.5 x 15 x 1.2mm, 6x8 ball array, 0.8mm pitch
(1Gbit Dual Die devices) in
Cache Program removed from document. TFBGA55 package specifications added
(Figure 40., TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package
Outline
Package Mechanical
Test conditions modified for V
3V
Third part number corrected in
added to
modified. Definition of a Bad Block modified in
RoHS COMPLIANCE
Diagram
Document promoted from Preliminary Data to Full Datasheet status.
Automatic Page 0 Read at Power-Up option no longer available.
PC Demo board with simulation software removed from list of available development
tools.
R
Description of the family clarified in the
WSOP48 replaced with USOP48 package,
VFBGA63 (8.5 x 15 x 1mm) replaced with VFBGA63 (9 x 11 x 1mm) package,
TFBGA63 (8.5 x 15 x 1mm) replaced with TFBGA63 (9 x 11 x 1.2mm) package.
Changes to
CC
ref
Devices.
WLWH
changed to V
parameter added to
Chip Enable (E)
6.,
Table
and
modified.
Table 10., Copy Back Program
timing in
Figure
Table 21., AC Characteristics for
Table 7., Address Insertion, x16 Devices
Table
BLBH4
Table 25., TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch,
2.. changed to
Figure 19., Cache Program Operation
7.,
DD
21.,
modified, partly replaced by t
Table 20., AC Characteristics for Command, Address, Data
Figure 30., Read C Operation, One Page AC
and I
Figure 29.
Data).
paragraph clarified.
Table 18.
added to
CC
Figure 28., Read Electronic Signature AC
Table 16., Operating and AC Measurement
Table 28., Ordering Information
Operation, modified and note 2 modified. Note removed
RELATED DOCUMENTATION
OL
“Product
to I
Devices. Note added to
Table 1., Product
and V
DD
and
and
SUMMARY
Revision Details
.
Table 2.
Figure 32.
Table 1., Product
OH
Description” and Page Program Typical Timing
SUMMARY DESCRIPTION
parameters in
Addresses.
Operations.
DESCRIPTION.
WHBH1
modified.
Bad Block Management
List. 512 Mbit Dual Die information
modified.
Block Erase
Table 19., DC Characteristics,
and t
List, inserted on page 2.
removed. Only 00h Pointer
Figure 32., Block Erase AC
Read Electronic Signature
Scheme.
DD4
WHRL
section and reference
Figure 3., Logic Block
removed from
Waveform, removed.
min for 3V devices
last address cycle
section.
Conditions.
Waveform,
paragraph.
Input.
Table