NAND01G-A STMICROELECTRONICS [STMicroelectronics], NAND01G-A Datasheet - Page 31

• Manufacturer Part Number: NAND01G-A
• Description: 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Figure 21. Garbage Collection
Garbage Collection
When a data page needs to be modified, it is faster
to write to the first available page, and the previous
page is marked as invalid. After several updates it
is necessary to remove invalid pages to free some
memory space.
To free this memory space and allow further pro-
gram operations it is recommended to implement
a Garbage Collection algorithm. In a Garbage Col-
lection software the valid pages are copied into a
free area and the block containing the invalid pag-
es is erased (see
Wear-leveling Algorithm
For write-intensive applications, it is recommend-
ed to implement a Wear-leveling Algorithm to
monitor and spread the number of write cycles per
block.
In memories that do not use a Wear-Leveling Algo-
rithm not all blocks get used at the same rate.
Blocks with long-lived data do not endure as many
write cycles as the blocks with frequently-changed
data.
The Wear-leveling Algorithm ensures that equal
use is made of all the available write cycles for
each block. There are two wear-leveling levels:
The Second Level Wear-leveling is triggered when
the difference between the maximum and the min-
imum number of write cycles per block reaches a
specific threshold.
First Level Wear-leveling, new data is
programmed to the free blocks that have had
the fewest write cycles
Second Level Wear-leveling, long-lived data is
copied to another block so that the original
block can be used for more frequently-
changed data.
Figure
Invalid
Valid
Page
Page
21.).
Old Area
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
(Erased)
Free
Page
Error Correction Code
An Error Correction Code (ECC) can be imple-
mented in the Nand Flash memories to identify
and correct errors in the data.
For every 2048 bits in the device it is recommend-
ed to implement 22 bits of ECC (16 bits for line par-
ity plus 6 bits for column parity).
An ECC model is available in VHDL or Verilog.
Contact the nearest ST Microelectronics sales of-
fice for more details.
Figure 22. Error Detection
New ECC generated
XOR previous ECC
22 bit data = 0
with new ECC
New Area (After GC)
during read
YES
All results
No Error
= zero?
NO
11 bit data = 1
Correctable
YES
= zero?
>1 bit
Error
AI07599B
NO
1 bit data = 1
ECC Error
31/57
ai08332