NAND01G-A STMICROELECTRONICS [STMicroelectronics], NAND01G-A Datasheet - Page 27

• Manufacturer Part Number: NAND01G-A
• Description: 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Block Erase
Erase operations are done one block at a time. An
erase operation sets all of the bits in the ad-
dressed block to ‘1’. All previous data in the block
is lost.
An erase operation consists of three steps (refer to
Figure
1. One bus cycle is required to setup the Block
2. Only three bus cycles for 512Mb and 1Gb
Figure 19. Block Erase Operation
Reset
The Reset command is used to reset the Com-
mand Interface and Status Register. If the Reset
command is issued during any operation, the op-
eration will be aborted. If it was a program or erase
operation that was aborted, the contents of the
memory locations being modified will no longer be
valid as the data will be partially programmed or
erased.
Erase command.
devices, or two for 128Mb and 256Mb devices
19.):
RB
I/O
Block Erase
Setup Code
60h
Block Address
Inputs
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Confirm
Code
D0h
3. One bus cycle is required to issue the confirm
Once the erase operation has completed the Sta-
tus Register can be checked for errors.
If the device has already been reset then the new
Reset command will not be accepted.
The Ready/Busy signal goes Low for t
the Reset command is issued. The value of t
depends on the operation that the device was per-
forming when the command was issued, refer to
Table 21.
are required to input the block address. The
first cycle (A0 to A7) is not required as only
addresses A14 to A26 (highest address
depends on device density) are valid, A9 to
A13 are ignored. In the last address cycle I/O2
to I/O7 must be set to V
command to start the P/E/R Controller.
(Erase Busy time)
for the values.
tBLBH3
Busy
Read Status Register
IL
70h
.
SR0
BLBH4
ai07593
BLBH4
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