HYB18L128160BC-7.5 QIMONDA [Qimonda AG], HYB18L128160BC-7.5 Datasheet - Page 18

• Manufacturer Part Number: HYB18L128160BC-7.5
• Description: DRAMs for Mobile Applications 128-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

Table 10
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
2.4.5
Figure 11
Subsequent to programming the mode register with CAS latency and burst length, READ bursts are initiated with
a READ command, as shown in
read operations and therefore are omitted from all subsequent timing diagrams.
The starting column and bank addresses are provided with the READ command and Auto Precharge is either
enabled or disabled for that burst access. If Auto Precharge is enabled, the row being accessed starts precharge
at the completion of the burst, provided t
following illustrations, Auto Precharge is disabled.
Data Sheet
Parameter
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
no. of clock cycles = specified delay / clock period; round up to next integer.
Timing Parameters for ACTIVE Command
READ
READ Command
Figure
11. Basic timings for the DQs are shown in
RAS
has been satisfied. For the generic READ commands used in the
Symbol
t
t
t
RC
RCD
RRD
18
67
19
15
min.
- 7.5
Functional DescriptionCommands
HY[B/E]18L128160B[C/F]-7.5
—
—
—
max.
128-Mbit Mobile-RAM
Figure
05282004-NZNK-8T0D
12; they apply to all
Rev. 1.71, 2007-01
ns
ns
ns
Units
1)
Notes