HYB18L128160BC-7.5 QIMONDA [Qimonda AG], HYB18L128160BC-7.5 Datasheet - Page 20

• Manufacturer Part Number: HYB18L128160BC-7.5
• Description: DRAMs for Mobile Applications 128-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

Table 11
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
During READ bursts, the valid data-out element from the starting column address is available following the CAS
latency after the READ command. Each subsequent data-out element is valid nominally at the next positive clock
edge. Upon completion of a READ burst, assuming no other READ command has been initiated, the DQs go to
High-Z state.
Figure 13
Figure 13
Data Sheet
Parameter
Access time from CLK
DQ low-impedance time from CLK
DQ high-impedance time from CLK
Data out hold time
DQM to DQ High-Z delay (READ Commands)
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command period
PRECHARGE command period
no. of clock cycles = specified delay / clock period; round up to next integer.
and
Timing Parameters for READ
Single READ Burst (CAS Latency = 2)
Figure 14
show single READ bursts for each supported CAS latency setting.
CL = 3
CL = 2
Symbol
t
t
t
t
t
t
t
t
t
t
AC
AC
LZ
HZ
OH
DQZ
RC
RCD
RAS
RP
20
—
—
1.0
3.0
2.5
—
67
19
45
19
min.
- 7.5
Functional DescriptionCommands
HY[B/E]18L128160B[C/F]-7.5
5.4
6.0
—
7.0
–
2
—
—
100k
—
max.
128-Mbit Mobile-RAM
05282004-NZNK-8T0D
Rev. 1.71, 2007-01
ns
ns
ns
ns
ns
t
ns
ns
ns
ns
CK
Units
—
—
—
—
1)
Notes