SE97 NXP [NXP Semiconductors], SE97 Datasheet - Page 12

• Manufacturer Part Number: SE97
• Description: DDR memory module temp sensor with integrated SPD, 3.3 V
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SE97_5
Product data sheet
7.7 SMBus time-out
7.8 SMBus Alert Response Address (ARA)
feature defaults to being enabled and can be programmed to disable. These registers are
required to be initialized before the device can properly function. Except for the SPD,
which does not have any programmable registers, and does not need to be initialized.
Table 4
registers.
Table 4.
The SE97 supports SMBus time-out feature. If the host holds SCL LOW between 25 ns
and 35 ms, the SE97 would reset its internal state machine to the bus IDLE state to
prevent the system bus hang-up. This feature is turned on by default. The SMBus time-out
is disabled by writing a ‘1’ to bit 7 of register 22h.
Remark: When SMBus time-out is enabled, the I
the SMBus time-out specification limit of 10 kHz.
The SE97 has no SCL driver, so it cannot hold the SCL line LOW.
Remark: SMBus time-out works over the entire supply range of 1.7 V to 3.6 V unless the
shutdown bit (SHMD) is set and turns off the oscillator.
The SE97 supports SMBus ALERT when it is programmed for the Interrupt mode and
when the EVENT polarity bit is set to ‘0’. The EVENT pin can be ANDed with other
EVENT or interrupt signals from other slave devices to signal their intention to
communicate with the host controller. When the host detects EVENT or other interrupt
signal LOW, it issues an ARA to which a slave device would respond with its address.
When there are multiple slave devices generating an ALERT the SE97 performs bus
arbitration with the other slaves. If it wins the bus, it responds to the ARA and then clears
the EVENT pin.
Remark: Either in comparator mode or when the SE97 crosses the critical temperature,
the host must also read the EVENT status bit and provide remedy to the situation by
bringing the temperature to within the alarm window or below the critical temperature if
that bit is set. Otherwise, the EVENT pin will not get de-asserted.
Remark: In the SE97 the ARA is set to default ON. However, in the SE97B the ARA will
be set to default OFF since ARA is not anticipated to be used in DDR3 DIMM applications.
Register
01h
02h
03h
04h
22h
shows the default values and the example value to be programmed to these
Registers to be initialized
Default value
0000h
0000h
0000h
0000h
0000h
Rev. 05 — 6 August 2009
DDR memory module temp sensor with integrated SPD, 3.3 V
Example value
0209h
0550h
1F40h
05F0h
0000h
Description
Configuration register
Upper Boundary Alarm Trip register = 85 C
Lower Boundary Alarm Trip register = 20 C
Critical Alarm Trip register = 95 C
SMBus register = no change
•
•
•
2
C-bus minimum bus speed is limited by
hysteresis = 1.5 C
EVENT output = Interrupt mode
EVENT output is enabled
© NXP B.V. 2009. All rights reserved.
SE97
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