SE97 NXP [NXP Semiconductors], SE97 Datasheet - Page 20

• Manufacturer Part Number: SE97
• Description: DDR memory module temp sensor with integrated SPD, 3.3 V
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 7.
Instructions with R/W bit = 1.
SE97_5
Product data sheet
Status
Permanently
protected
Protected with
RWP
Not protected
Acknowledge when reading the write protection
7.10.2.3 Read Permanent Write Protection (RPWP), Read Reversible Write Protection
7.10.3.1 Current address read
7.10.3.2 Selective read
7.10.3 Read operations
Instruction
RPWP, RRWP or
RCRWP
RRWP
RCRWP
RPWP
RPWP, RRWP or
RCRWP
(RRWP), and Read Clear Reversible Write Protection (RCRWP)
Read PWP, RWP, and CRWP allow the SE97 to be read in write protection mode. The
instruction format is the same as that of the write protection except that the 8
set to 1.
the instructions are issued.
In Standby mode, the SE97 internal address counter points to the data byte immediately
following the last byte accessed by a previous operation. If the ‘previous’ byte was the last
byte in memory, then the address counter will point to the first memory byte, and so on. If
the SE97 decodes a slave address with a ‘1’ in the R/W bit position
issue an Acknowledge in the ninth clock cycle and will then transmit the data byte being
pointed at by the address counter. The master can then stop further transmission by
issuing a No Acknowledge on the ninth bit then followed by a STOP condition.
The read operation can also be started at an address different from the one stored in the
address counter. The address counter can be ‘initialized’ by performing a ‘dummy’ write
operation
bit set to ‘0’) and the desired byte address. Instead of following-up with data, the master
then issues a second START, followed by the ‘Current Address Read’ sequence, as
described in
Fig 18. Current address read timing
Figure 17
(Figure
SDA
Section
START condition
S
19). The START condition is followed by the slave address (with the R/W
ACK
NACK
NACK
ACK
ACK
ACK
shows the instruction format, while
1
7.10.3.1.
slave address (memory)
Rev. 05 — 6 August 2009
0
DDR memory module temp sensor with integrated SPD, 3.3 V
1
Address
not significant
not significant
not significant
not significant
not significant
0
A2 A1 A0
R/W acknowledge
1
ACK
NACK
NACK
NACK
NACK
NACK
A
from slave
Data byte
not significant
not significant
not significant
not significant
not significant
data from memory
Table 7
shows the responses when
no acknowledge
from master
STOP condition
(Figure
ACK
NACK
NACK
NACK
NACK
NACK
002aab251
© NXP B.V. 2009. All rights reserved.
A
18), it will
P
th
bit, R/W, is
SE97
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