AT32UC3L064_11 ATMEL [ATMEL Corporation], AT32UC3L064_11 Datasheet - Page 96

• Manufacturer Part Number: AT32UC3L064_11
• Description: 32-bit Atmel AVR Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

10.4.8
10.4.9
32099HS–12/2011
AST
WDT
1. AST wake signal is released one AST clock cycle after the BUSY bit is cleared
1. Clearing the WDT in window mode
2. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will
3. VERSION register reads 0x400
4. WDT Control Register does not have synchronization feedback
RC120MVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
After writing to the Status Clear Register (SCR) the wake signal is released one AST clock
cycle after the BUSY bit in the Status Register (SR.BUSY) is cleared. If entering sleep mode
directly after the BUSY bit is cleared the part will wake up immediately.
Fix/Workaround
Read the Wake Enable Register (WER) and write this value back to the same register. Wait
for BUSY to clear before entering sleep mode.
In window mode, if the WDT is cleared 2
the counter will be cleared, but will not exit the window. If this occurs, the SR.WINDOW bit
will not be cleared after clearing the WDT.
Fix/Workaround
Check SR.WINDOW immediately after clearing the WDT. If set then clear the WDT once
more.
issue a Watchdog reset
If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi-
ately issue a Watchdog reset.
Fix/Workaround
Use twice as long timeout period as needed and clear the WDT counter within the first half
of the timeout period. If the WDT counter is cleared after the first half of the timeout period,
you will get a Watchdog reset immediately. If the WDT counter is not cleared at all, the time
before the reset will be twice as long as needed.
The VERSION register reads 0x400 instead of 0x402.
Fix/Workaround
None.
When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN),
Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchro-
nizer is started to propagate the values to the WDT clcok domain. This synchronization
takes a finite amount of time, but only the status of the synchronization of the EN bit is
reflected back to the user. Writing to the synchronized fields during synchronization can lead
to undefined behavior.
Fix/Workaround
-When writing to the affected fields, the user must ensure a wait corresponding to 2 clock
cycles of both the WDT peripheral bus clock and the selected WDT clock source.
-When doing writes that changes the EN bit, the EN bit can be read back until it reflects the
written value.
TBAN
CLK_WDT cycles after entering the window,
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