STM32F101X6_08 STMICROELECTRONICS [STMicroelectronics], STM32F101X6_08 Datasheet - Page 55

• Manufacturer Part Number: STM32F101X6_08
• Description: Access line, advanced ARM-based 32-bit MCU with Flash memory, six 16-bit timers, ADC and seven communication interfaces
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STM32F101xx
SPI interface characteristics
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
summarized in
Refer to
function characteristics (NSS, SCK, MOSI, MISO).
Table 40.
1. Remapped SPI1 characteristics to be determined.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
t
t
t
t
dis(SO)
t
t
t
w(SCKH)
v(SO)
t
w(SCKL)
a(SO)
v(MO)
1/t
su(NSS)
t
Symbol
t
t
t
t
h(NSS)
su(MI)
t
h(MO)
the data.
the data in Hi-Z
su(SI)
h(MI)
h(SO)
t
t
h(SI)
r(SCK)
f(SCK)
f
c(SCK)
SCK
(2)(3)
(2)(1)
(2)(1)
(2)
(2)(4)
(2)
(2)
(2)
(2)
(2)
(2)
Section 5.3.12: I/O port characteristics
(2)
(2)
(2)
SPI characteristics
SPI clock frequency
SPI clock rise and fall
time
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Master mode
Data input setup time
Slave mode
Data input hold time
Master mode
Data input hold time
Slave mode
Data output access time
Data output disable time Slave mode
Data output valid time
Data output valid time
Data output hold time
Table
Parameter
7.
(1)
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Master mode, f
presc = 4
SPI1
SPI2
SPI1
SPI2
Slave mode, f
presc = 4
Slave mode, f
Slave mode (after enable edge)
Master mode (after enable
edge)
Slave mode (after enable edge)
Master mode (after enable
edge)
PCLKx
Conditions
frequency and V
for more details on the input/output alternate
PCLK
PCLK
PCLK
Table 40
= 24 MHz
= 36 MHz,
= 36 MHz,
are derived from tests
DD
Electrical characteristics
supply voltage conditions
4 t
Min
18
10
PCLK
25
50
0
1
5
1
1
5
4
0
3
0
0
4 t
Max
18
60
55
25
18
PCLK
3
8
MHz
Unit
55/74
ns