STM32F101X6_08 STMICROELECTRONICS [STMicroelectronics], STM32F101X6_08 Datasheet - Page 9

• Manufacturer Part Number: STM32F101X6_08
• Description: Access line, advanced ARM-based 32-bit MCU with Flash memory, six 16-bit timers, ADC and seven communication interfaces
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STM32F101xx
2.2
Overview
ARM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F101xx access line family having an embedded ARM core, is therefore
compatible with all ARM tools and software.
Embedded Flash memory
Up to 128 Kbytes of embedded Flash is available for storing programs and data.
Embedded SRAM
Up to 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
Nested vectored interrupt controller (NVIC)
The STM32F101xx access line embeds a nested vectored interrupt controller able to handle
up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3)
and 16 priority levels.
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This hardware block provides flexible interrupt management features with minimal interrupt
latency.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detectors lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect external line with pulse
width lower than the Internal APB2 clock period. Up to 80 GPIOs are connected to the 16
external interrupt lines.
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
®
Cortex
TM
-M3 core with embedded Flash and SRAM
Description
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