AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 107
AT83EC5123
Manufacturer Part Number
AT83EC5123
Description
(AT8xx512x) Smart Card Reader ICs
Manufacturer
ATMEL Corporation
Datasheet
1.AT83EC5123.pdf
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Serial Peripheral Status Register
(SPSTA)
4202B–SCR–07/03
The
conditions:
•
•
•
Table 80. Serial Peripheral Status and Control Register - SPSTA (C4h)
Reset Value = 00X0XXXXb
Number
3 - 0
SPIF
Bit
Data transfer complete
Write collision
Inconsistent logic level on SS pin (mode fault error)
Serial Peripheral Status Register contains flags to signal the following
7
6
5
4
7
Mnemonic
SSERR
WCOL
MODF
WCOL
SPIF
Bit
6
-
Mode Description
R/W
RW
SSERR
R
R
R
R
5
Serial Peripheral data transfer flag
Clear by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
Write Collision flag
Cleared by hardware to indicate that no collision has occurred or has
been approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
Synchronous Serial Slave Error flag
Set by hardware when SS is modified before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic
level, or has been approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level
Reserved
The value read from this bit is indeterminate. Do not change these bits.
MODF
4
3
-
2
AT8xC5122/23
-
1
-
0
-
9
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