AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 34

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AT83EC5123

Manufacturer Part Number
AT83EC5123
Description
(AT8xx512x) Smart Card Reader ICs
Manufacturer
ATMEL Corporation
Datasheet
Registers
34
AT8xC5122/23
Table 31. Clock Selection Register - CKSEL (S:85h)
Reset Value = XXXX XXX0b
Table 32. Clock Reload Register - CKRL (S:97h)
Reset Value = XXXX 1111b
Table 33. Clock Configuration Register 1 - CKCON1 (S:AFh) only for AT8xC5122
Reset Value = XXXX XXX0b
Bit Number Bit Mnemonic Description
Bit Number Bit Mnemonic Description
Bit Number Bit Mnemonic Description
7 - 4
7 - 4
7:1
3:0
7
7
7
-
0
-
-
3
0
CKRL3:0
6
6
6
SPIX2
-
-
-
CKS
-
-
-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
CPU Oscillator Select Bit
Set this bit to connect CPU and Peripherals to PLL output.
Clear this to to connect CPU and Peripherals to XTAL1 clock input.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Clock Reload register
Prescaler1 value
F
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
SPI clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Cleared to bypass the PR1 prescaler.
Set to select the PR1 output for this peripheral.
ck_cpu
5
5
5
-
-
-
=[ 1 / 2*(16-CKRL)] * F
4
4
4
-
-
-
CKRL3
3
3
3
-
-
ck_XTAL1
CKRL2
2
2
2
-
-
CKRL1
1
1
1
-
-
4202B–SCR–07/03
CKRL0
SPIX2
CKS
0
0
0

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