AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 94

• Manufacturer Part Number: AT83EC5123
• Description: (AT8xx512x) Smart Card Reader ICs
• Manufacturer: ATMEL Corporation

Modes 2 and 3
Transmission
(Modes 1, 2 and 3)
Reception
(Modes 1, 2 and 3)
Framing Error Detection
(Modes 1, 2 and 3)
94
AT8xC5122/23
Modes 2 and 3
Start bit
Figure 57. Data Frame Format (Mode 1)
Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 58)
consists of 11 bits: one start bit, eight data bits (transmitted and received LSB first), one
programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin
and received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON
register. On transmit, the ninth data bit is written to TB8 bit in SCON register. Alterna-
tively, you can use the ninth bit as a command/data flag.
Figure 58. Data Frame Format (Modes 2 and 3)
To initiate a transmission, write to SCON register, setting SM0 and SM1 bits according
to Figure 51 on page 92, and setting the ninth bit by writing to TB8 bit. Then, writing the
byte to be transmitted to SBUF register starts the transmission.
To prepare for a reception, write to SCON register, setting SM0 and SM1 bits according
to Figure 51 on page 92, and setting REN bit. The actual reception is then initiated by a
detected high-to-low transition on the RXD pin.
Framing error detection is provided for the three asynchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register as shown in
Figure 59.
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two devices. If a valid stop bit is not found, the software sets FE bit in
SCON register.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a chip reset clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When the framing error detection feature is enabled, RI rises on
stop bit instead of the last data bit as detailed in Figure 57 and Figure 58.
Figure 59. Framing Error Block Diagram
Mode 1
D0
D1
Start bit
Framing Error
D2
Controller
D0
D3
9-bit data
D1
D4
FE
D2
D5
SM0
D3
8-bit data
D6
SMOD0
PCON.6
1
0
D4
D7
D5
D8
SM0/FE
SCON.7
D6
Stop bit
D7
Stop bit
4202B–SCR–07/03