AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 30

• Manufacturer Part Number: AT83EC5123
• Description: (AT8xx512x) Smart Card Reader ICs
• Manufacturer: ATMEL Corporation

CK_ISO and CK_CPU selection
30
AT8xC5122/23
The CPU and peripherals clocks frequencies are defined in the table below.
Two conditions must be present for an optimal work of the SCIB:
•
•
If the CK_CPU <= 4/3 * CK_ISO, the SCIB doesn’t work.
If the CK_CPU >= 6* CK_ISO, the programmer must take care in three cases:
•
•
•
To avoid any trouble, a delay must be added between the two accesses on the SCIB
register. The SCIB must complete the first read (or write) operation before to receive the
second. A solution is to add NOP (no operation) instructions. The number of NOP to add
depends of the rate between CK_CPU and CK_ISO (see table below).
CKS
0
0
1
1
CK_CPU > 4/3 * CK_ISO and
CK_CPU < 6 * CK_ISO.
Read (or write) operation on a SCIB register followed immediatly with an other Read
(or write) operation on the same register.
Read (or write) operation on a SCIB register followed immediatly with an other Read
(or write) operation on a linked register. The list of linked registers is in the table
below.
Write operation on a register of the list below followed immediatly with a read
operation on a SCIB register.
min CLK_CPU
CLK_CPU >= 6 * CLK_ISO
CLK_CPU >= 12* CLK_ISO
X2
0
1
0
1
Linked registers
Write in SCICR and after read of SCETU0-1
Write in SCTBUF and after read of SCISR
Wait after Write operation on this registers
SCICR, SCIER, SCETU0-1,SCGT0-1,
SCWT0-3,SCCON
max CLK_CPU
CLK_CPU <= 12 * CLK_ISO
CLK_CPU <= 16 * CLK_ISO
F
F
F
F
Not allowed
CK_CPU
CK_XTAL1
CK_XTAL1
CK_PLL
/(2*(16-CKRL))
and F
/(2*(16-CKRL))
CK_IDLE
Number of
CPU cycles to add
12 ( example 2 NOP)
6 ( example1 NOP)
4202B–SCR–07/03