AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 92

• Manufacturer Part Number: AT83EC5123
• Description: (AT8xx512x) Smart Card Reader ICs
• Manufacturer: ATMEL Corporation

Transmission (Mode 0)
Reception (Mode 0)
92
AT8xC5122/23
Figure 51. Serial I/O Port Block Diagram (Mode 0)
To start a transmission mode 0, write to SCON register clearing bits SM0, SM1.
As shown in Figure 52, writing the byte to transmit to SBUF register starts the transmis-
sion. Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle
composed of a high level then low level signal on TXD. During the eighth clock cycle the
MSB (D7) is on the RXD pin. Then, hardware drives the RXD pin high and asserts TI to
indicate the end of the transmission.
Figure 52. Transmission Waveforms (Mode 0)
To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI bits
and setting the REN bit.
As shown in Figure 53, Clock is pulsed and the LSB (D0) is sampled on the RXD pin.
The D0 bit is then shifted into the shift register. After eight sampling, the MSB (D7) is
shifted into the shift register, and hardware asserts RI bit to indicate a completed recep-
tion. Software can then read the received byte from SBUF register.
Figure 53. Reception Waveforms (Mode 0)
Write to SCON
Write to SBUF
SCON.6
SCON.1
M3 M2 M1 M0
SM1
Mode Decoder
TI
Controller
RXD
TXD
RXD
TXD
Mode
RI
TI
SCON.7
SCON.0
SM0
RI
Set REN, Clear RI
D0
D0
D1
D1
CLOCK
IBRG
CK_
T1
D2
D2
D3
D3
SBUF Rx SR
SBUF Tx SR
Baud Rate
Controller
D4
D4
D5
D5
D6
D6
D7
D7
4202B–SCR–07/03
RXD
TXD