ZL50015GAC ZARLINK [Zarlink Semiconductor Inc], ZL50015GAC Datasheet - Page 54

• Manufacturer Part Number: ZL50015GAC
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

6 - 5
External Read/Write Address: 0000
Reset Value: 0000
Bit
4
3
2
15
0
14
CKIN1 - 0
0
VAREN
MBPE
Name
OSB
DPLLEN
H
SLV_
13
Input Clock (CKi) and Frame Pulse (FPi) Selection
The MODE_4M0 and MODE_4M1 pins, as described in “Pin Description” on page 13,
should also be set to define the input clock mode.
Variable Delay Mode Enable
When this bit is low, the variable delay mode is disabled on a device-wide basis.
When this bit is high, the variable delay mode is enabled on a device-wide basis.
Memory Block Programming Enable
When this bit is high, the connection memory block programming mode is enabled to
program the connection memory. When it is low, the memory block programming mode is
disabled.
Output Stand By Bit:
This bit enables the STio0 - 15 and the STOHZ0 -7 serial outputs. The following table
describes the HiZ control of the serial data outputs:
Note: Unused output streams are tristated (STio = HiZ, STOHZ = Driven High). Refer to
SOCR0 - 15 (bit2 - 0).
OPM
12
1
RESET
Table 17 - Control Register (CR) Bits (continued)
H
Pin
OPM
0
1
1
1
1
11
0
CKi_
10
LP
SRSTSW
(in SRR)
CKIN1 - 0
X
1
0
0
0
00
01
10
11
FPIN
POS
Zarlink Semiconductor Inc.
9
ZL50015
ODE
CKINP
Pin
X
X
0
1
1
8
54
FPi Active Period
OSB
FPINP
Bit
X
X
X
0
1
7
Description
122 ns
244 ns
61 ns
CKIN
(Controlled by CM)
6
1
STio0 - 15
Reserved
Active
CKIN
HiZ
HiZ
HiZ
HiZ
5
0
VAR
EN
4
16.384 MHz
8.192 MHz
4.096 MHz
MBPE
CKi
3
(Controlled by CM)
STOHZ0 - 7
Driven High
Driven High
Driven High
Driven High
OSB
2
Active
Data Sheet
MS1
1
MS0
0