ZL50015GAC ZARLINK [Zarlink Semiconductor Inc], ZL50015GAC Datasheet - Page 79

• Manufacturer Part Number: ZL50015GAC
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

External Read/Write Address: 006C
Reset Value: 0002
15
15 - 3
0
2 - 0
External Read/Write Address: 0100
Reset Value: 0000
15 - 9
Bit
5 - 4
8 - 6
15
0
Bit
14
0
14
0
13
0
OJP2 - 0
STIN[n]SMP1 - 0
Unused
STIN[n]BD2 - 0
Name
13
H
H
0
12
0
Unused
Name
Table 43 - Stream Input Control Register 0 - 15 (SICR0 - 15) Bits
11
0
12
0
Reserved
In normal functional mode, these bits MUST be set to zero.
Output Jitter Performance Bits
These bits are used to control the DPLL output jitter performance with respect to the
noise received through the output pins. The higher value (unsigned) means more
filtering, while zero means filter bypass. The default value of 2
performance for most circumstances.
10
Table 42 - Output Jitter Control Register (OJCR) Bits
0
H
- 010F
11
H
0
9
0
Reserved
In normal functional mode, these bits MUST be set to zero
Input Stream[n] Bit Delay Bits.
The binary value of these bits refers to the number of bits that the input stream
will be delayed relative to FPi. The maximum value is 7. Zero means no delay.
Input Data Sampling Point Selection Bits
H
STIN[n]SMP1-0
STIN[n]
10
BD2
0
8
00
01
10
11
9
STIN[n]
0
Zarlink Semiconductor Inc.
BD1
7
ZL50015
8
0
STIN[n]
BD0
(2.048 Mbps, 4.096 Mbps, 8.192 Mbps
79
6
7
0
STIN[n]
SMP1
Description
5
Sampling Point
6
0
Description
streams)
3/4 point
1/4 point
2/4 point
4/4 point
STIN[n]
SMP0
4
5
0
STIN[n]
DR3
4
0
3
3
0
STIN[n]
DR2
2
.
OJP2
2
H
STIN[n]
Sampling Point
DR1
gives the best
(16.384 Mbps
1
streams)
2/4 point
4/4 point
OJP1
Data Sheet
1
STIN[n]
DR0
0
OJP0
0