ZL50015GAC ZARLINK [Zarlink Semiconductor Inc], ZL50015GAC Datasheet - Page 63

• Manufacturer Part Number: ZL50015GAC
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Note: [n] denotes input stream from 0 - 15.
External Read/Write Address: 0040
Reset Value: 0000
15 - 0
15
15-6
0
Bit
4-2
Bit
External Read Address: 00013
Reset Value: 0000
5
1
0
BER
L15
15
14
0
ST4_LIM
Unused
Unused
DPLL_
Name
RFRE
BERL[n]
BER
L14
IRM
Name
14
13
H
0
H
Table 25 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only
BER
L13
13
12
0
Reserved
In normal functional mode, these bits MUST be set to zero.
Stratum 4E Limits Select Bit
When this bit is high, the stratum 4E limits are used for reference monitoring (i.e.,
+/-64.713 ppm and +/-82.487 ppm over 10 seconds). When this bit is low, more relaxed
Relaxed Stratum 4E limits are used for reference monitoring (e.g., +/-240 ppm and
+/-250 ppm over 10 seconds). This is used in applications where a low quality clock
(+/-100 ppm) is used as a reference.
Reserved
In normal functional mode, these bits MUST be set to zero.
Reference Frequency Register Enable
When this bit is low, the reference frequency value used in the DPLL comes from
appropriate reference frequency detector. When this bit is high, the reference frequency
value comes from Reference Frequency Register (RFR).
DPLL Internal Reset Mode
When this bit is low, the DPLL module is in the operational state. When this bit is high,
the DPLL module is in the power saving mode. Registers are not reset and are still
accessible in the power saving mode.
BER Receiver Lock[n]
If BERL[n] is high, it indicates that BER Receiver of STi[n] is locked.
If BERL[n] is low, it indicates that BER Receiver of STi[n] is not locked.
BER
L12
12
H
H
11
Table 26 - DPLL Control Register (DPLLCR) Bits
0
BER
L11
11
10
0
BER
L10
10
9
0
Zarlink Semiconductor Inc.
BER
L9
9
ZL50015
8
0
BER
L8
8
63
7
0
BER
L7
7
Description
Description
6
0
BER
L6
6
ST4_
LIM
BER
5
L5
5
BER
L4
4
0
4
BER
L3
3
3
0
BER
L2
2
2
0
BER
L1
1
Data Sheet
RFRE
1
BER
L0
0
DPLL
_IRM
0