ZL50015GAC ZARLINK [Zarlink Semiconductor Inc], ZL50015GAC Datasheet - Page 69

• Manufacturer Part Number: ZL50015GAC
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Note: The default value is ±56 ppm (’h099F/CFN = 56 ppm).
15 - 13
External Read/Write Address: 0049
External Read/Write Address: 004B
Reset Value: 099F
12 - 0
Reset Value: 0000
15 - 8
Bit
Bit
15
15
7
0
0
14
14
0
SRL12 - 0
0
Unused
Unused
Name
Name
MTR
H
H
13
13
(see Note)
0
0
SRL
Reserved
In normal functional mode, these bits MUST be set to zero.
Slew Rate Limit Bits
The binary value of these bits defines the maximum rate of DPLL phase change (phase
slope), where the phase represents difference between the input reference and output
feedback clock. Defined in same units as CFN (unsigned).
Reserved
In normal functional mode, these bits MUST be set to zero.
MTIE Reset
When this bit is low, the MTIE circuit applies a phase offset between the reference input
clock and the DPLL output clock and the phase offset value is maintained. When this bit
is high, MTIE circuit is in its reset state and the phase offset value is reset to zero,
causing alignment of the DPLL output clocks to nearest edge of the selected input
reference.
12
12
Table 34 - Reference Change Control Register (RCCR) Bits
12
0
H
H
Table 33 - Slew Rate Limit Register (SRLR) Bits
SRL
11
11
11
0
SRL
10
10
10
0
SRL
9
9
9
0
Zarlink Semiconductor Inc.
ZL50015
SRL
8
8
8
0
69
MTR
SRL
7
7
7
Description
Description
SRL
PRS
6
6
6
1
PRS
SRL
5
5
5
0
PMS
SRL
4
4
4
2
PMS
SRL
3
3
3
1
PMS
SRL
2
2
2
0
Data Sheet
FDM
SRL
1
1
1
1
FDM
SRL
0
0
0
0