AM7968 AMD [Advanced Micro Devices], AM7968 Datasheet - Page 15

• Manufacturer Part Number: AM7968
• Description: TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface)
• Manufacturer: AMD [Advanced Micro Devices]

Am7968 Encoder/Am7969 Decoder
To guarantee that the Am7969’s PLL can stay locked
onto an incoming bit stream, the data encoding scheme
must provide an adequate number of transitions in each
data pattern. This implies a limit on the maximum time
allowed between transitions. The TAXIchip set encod-
ing scheme is based on the ANSI X3T9.5 (FDDI) com-
mittee’s 4-bit/5-bit (4B/5B) code.
An ANSI X3T9.5 system used an 8-bit parallel data pat-
tern. This pattern is divided into two 4-bit nibbles which
are each encoded into a 5-bit symbol. Of the thirty-two
patterns possible with these five bits, sixteen are chosen
to represent the sixteen input Data patterns. Some of
the others are used as Command symbols. Those re-
maining represent invalid patterns that fail either the
run-length test or DC balance tests.
Transmitters in 8-bit mode use two 4B/5B encoders to
encode eight Data bits into a 10-bit pattern. In 9-bit
mode, Transmitters use one 5B/6B encoder and one
4B/5B encoder to code nine Data bits into an 11-bit pat-
tern. In 10-bit mode, two 5B/6B encoders are used to
change ten bits of Data into a 12-bit pattern (see Tables
1 and 2 for encoding patterns).
The Am7968 Transmitter further encodes all symbols
using NRZI (Non Return to Zero, Invert on Ones). NRZI
represents a “1” by a transition and a “0” by the lack of
transition. In this system a “1” can be a HIGH-to-LOW or
LOW-to-HIGH transition. This combination of 4B/5B
and NRZI encoding ensures at least two transitions per
symbol and permits a maximum of three consecutive
non-transition bit times. The Am7969 then uses the
same method to decode incoming symbols so that the
whole encoding/decoding process is transparent to
the user.
Most Serially transmitted data patterns with this code
will have the same average amount of HIGH and LOW
times. This near DC balance minimizes pattern-sensi-
tive decoding errors which are caused by jitter in AC-
coupled systems.
Operational Modes
In normal operational mode, a single Transmitter/
Receiver pair is used to transfer 8, 9, or 10 bits of parallel
Data over a private serial link. (On the Am7968, the TLS
pin is tied to ground and TSERIN is left unconnected).
On the Am7969, CNB must be connected to the CLK
output. The Am7969 Receiver continuously deserial-
izes the incoming bit stream, decodes the resulting pat-
terns, and saves parallel data at its output latches (see
Figure 3).
Local mode provides a fast and efficient parallel
throughout because data can be transferred on every
clock cycle. On the other hand, it is not necessary for the
host to match the byte rate set by the Transmitter’s crys-
tal oscillator; the Am7968 automatically sends a Sync
Am7968/Am7969
pattern during each clock cycle in which no new Data or
Command messages are being transmitted.
Cascade Mode (for –125 only)
For very wide parallel buses, TAXI Receiver’s (commer-
cial temperature parts only) can be Cascaded. The
Am7969 Receivers all have their SERIN+ and SERIN–
pins connected to the media (or an optical data link).
IGM of each Am7969 is connected to CNB of its down-
stream neighbor or is left unconnected on the Receiver
farthest downstream. CNB of the first Receiver is tied
HIGH, making this device the only Receiver in the chain
that can act on the first non-Sync pattern in a message
(see below).
Each TAXIchip Receiver monitors the serial link and a
special acknowledgment scheme is used to direct sym-
bols into each of the Am7969s. When a Catch-Next-
Byte ( CNB ) input is HIGH, the Receiver will capture the
next non-Sync symbol from the serial link. At this point,
the device forces its I-Got-Mine ( IGM ) pin HIGH to tell
the downstream Receiver to capture the next symbol.
The Receiver then waits for the Sync symbol or for its
CNB to be set LOW before transferring the message to
its output latch. IGM is forced LOW whenever a Sync
byte is detected or when CNB goes LOW. This IGM -
CNB exchange continues down the chain until the last
Receiver captures its respective byte. The next byte to
appear on the serial link will be a Sync symbol which is
detected by all of the cascaded Am7969s. On the follow-
ing Clock cycle their messages are transferred to the
output latch of each device and sent to the receiving
host. IGM pins on all Receivers are also set LOW when
the first half of the Sync symbol is detected.
Asynchronous Operation
Inputs to the Am7968 Transmitter Input Latch can be
asynchronous to its internal clock. Data STRB will latch
data into the Am7968 Transmitter and an internal clock
will transfer the data to the Encoder Latch at the first
byte boundary. Data can be entered at any rate less
than the maximum transfer rate without regard to actual
byte boundaries. As data rates approach the TAXI
BYTE RATE, care must be taken to insure that the 2
BYTE FIFO inside TAXI Transmitter is not over filled.
STRB/ACK handshake will assure that every byte is
transferred correctly. At higher byte rates, where delays
and setup/hold times make the STRB/ACK handshake
impractical, STRB should be synchronized with CLK .
Synchronous Operation
The Transmitter may be strobed synchronous by tying
the strobe to the input clock. When doing this a provision
should be make to inhibit the strobe periodically to en-
sure proper byte alignment. In the absence of a strobe,
Syncs will be transmitted on the serial link which will al-
low the receiver to re-align the byte boundaries. In addi-
tion it is essential that the delay between the falling edge
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