SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 18

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

CD1283 — IEEE 1284-Compatible Parallel Interface
18
NOTE: The above five parallel handshake signals are driven by the slave in an IEEE Std 1284 interface, and as such are
EBDIR
PDBEN
Symbol
outputs from the CD1283. Their functions depend on the transfer protocol selected. Refer to the IEEE Std 1284-1994
document for protocol functions. (See
Pin No.
49
51
Type
O
O
EXTERNAL BUFFER DIRECTION: This signal is controlled by the internal parallel
port control state machine and can be used to control the direction of an external buffer
connected to the Parallel Port data bus. An external buffer might be desirable in
applications that require higher drive capacity than that provided by the CD1283.
EBDIR can be used in conjunction with PDBEN to control this buffer. EBDIR is a logic
‘0’ when the parallel data bus is in an output mode, and a logic ‘1’ when in an input
mode. It can be connected directly to the direction control input of a 74245-type device.
PARALLEL DATA BUS ENABLE: This signal can control a buffer on the Parallel Port
data lines in applications requiring more signal-drive capability than provided by the
CD1283. PDBEN is controlled by the internal Parallel Port control state machine.
When low, the parallel port data bus is not driving; when high, the port is in output
mode and is actively driving. PDBEN will toggle between the on and off states during
output modes and is only active (high) while the data bus pins are in the active driving
state. PDBEN can be logically connected to the enable control of 74245 (or equivalent)
bidirectional buffers (see
Section 5.4.1 on page 33
Section 5.9
Description (Sheet 3 of 3)
for ordering information.)
and
Figure
11).
Datasheet