SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 53

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

7.0
7.1
7.1.1
7.1.2
Datasheet
Register Name: AER
Register Description: Access Enable
Access: R/W
Register Name: GFRCR
Register Description: Global Firmware Revision Code
Access: R/W
Bit 7
Bit 7
X
Detailed Register Descriptions
This section presents a detailed description of each register. Registers have two formats: full eight
bits, where the entire content defines a single function; or the register is a collection of bits,
grouped singly or in multiples, defining a function. In the second case, the descriptions divide the
register into its component parts and describe the bits individually. The registers are presented in
the same order as outlined in
other than ‘0’ are read, program execution should not be affected or software compatibility with
future revisions will be uncertain.
Global Registers
Access Enable Register
The AER provides binary compatibility with the CD1284. Users must program this register with
the least-significant bits set to ‘0’ to access the parallel channel; however, to perform a device reset
through the RCR, AER must = 02h. The contents of the upper 5 bits should be ignored when read.
Global Firmware Revision Code Register
The GFRCR serves two purposes in the CD1283. First, it displays the revision number of the
firmware in the device. When a revision to the CD1283 is required, the revision number of the
firmware is increments by one. The revision code is 24 (hex) for the Revision D device, and 25
(hex) for the Revision E device.
Secondly, this register can be used by the system programmer as an indication of when the internal
processor has completed reset procedures, after either a power-on reset (through the RESET*
input) or a software global reset (through the reset command in the CCR). Immediately after the
reset operation begins, the internal CPU clears the register. When complete, and the CD1283 is
ready to accept host accesses, the register is loaded with the revision code.
Bit 6
Bit 6
X
Bit 5
Bit 5
X
Chapter
Firmware Revision Code
Bit 4
Bit 4
X
4.0. Bits defined as ‘0’ should not be modified and, if values
IEEE 1284-Compatible Parallel Interface — CD1283
Bit 3
Bit 3
X
Bit 2
Bit 2
0
Bit 1
Bit 1
8-Bit Hex Address: 68
8-Bit Hex Address: 4F
0
Default Value: XX
Default Value: 25
Bit 0
Bit 0
0
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