SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 60

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

CD1283 — IEEE 1284-Compatible Parallel Interface
7.3.5
60
Register Name: LIVR
Register Description: Local Interrupt Vector
Access: R/W
Bit 7
Bit
7:3
2:0
The computed value is rounded up to the next largest whole hex value, in this case ‘0x3000’. Load
HTVR with the most-significant 8 bits of this value, left-shifted two places since HTVR is a 14-bit
counter. This results in a value of ‘0xC0’. For 20 MHz, the value is computed to be ‘0x9C’ and for
16 MHz, the value is ‘0x7C’; values for other clocks can be easily computed in the same manner.
At reset, the HTVR defaults to a value of ‘0xFF’; this prevents the extremely short Timeouts that
occur if the register is cleared at device reset and not initialized.
A timeout causes a negotiation status change interrupt. This status is displayed as 0x22 in the
Negotiation Status Register (Host Timeout (bit 5), and the code for return to Compatibility mode
(0010) in the result code field). When Compatibility mode is reentered, the port control state
machine waits in a locked state until signals on the parallel port return to normal Compatibility
mode conditions.
For debug purposes, disable the host Timeout timer by setting PCR bits 2 and 3 (Host Timer Test
[1:0]). In this case, no Timeouts occur and the link can hang indefinitely while waiting for a host-
generated event.
Local Interrupt Vector Register
This read/write register can be initialized to any desired value and, when read in the normal context
(that is, not a service acknowledge context), the same value is returned. The upper 5 bits are copied
into the appropriate vector register, PIVR when the SVCACKP* signal is activated and
SVCREQP* is active. During this hardware-activated service acknowledge read cycle, the PIVR is
driven onto the data bus, DB[7:0]. Bits 7:3 come from LIVR and bits 2:0 are supplied by the
CD1283
appropriate service routine (typical in Motorola-type systems) or as a device identifier for systems
with multiple, daisy-chained CD1283s. Bits 2:0 are ignored. Initialization of this register is only
necessary if vectored interrupts are used.
User-Defined Interrupt Vector: Host software can use these five bits for any purpose appropriate to the
application. In some cases, these bits might define the rest of a complete interrupt response vector (Motorola-
type systems). In the case of daisy-chain systems made up of multiple CD1283s, these bits are used to define
the device number in the chain.
These bits are ‘don’t cares’.
Bit 6
(Section 7.2.2 on page 56
User-Defined Bits
Bit 5
25MHz
----------------- -
2048
=
Bit 4
12207
for details). This value can be used as a vector into the
10
Description
=
Bit 3
2FAF
16
Bit 2
X
Bit 1
8-Bit Hex Address: 18
X
Default Value: 00
Datasheet
Bit 0
X