SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 54

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

CD1283 — IEEE 1284-Compatible Parallel Interface
7.1.3
7.1.4
7.1.5
54
Register Name: GPDIR
Register Description: General-Purpose I/O Direction
Access: R/W
Register Name: GPIO
Register Description: General-Purpose I/O
Access: R/W
Register Name: PIR
Register Description: Parallel Interrupt
Access: R/W
PPireq
Data7
Bit 7
Bit 7
Bit 7
Dir7
General-Purpose I/O Direction Register
General-Purpose I/O Register
The GPDIR and GPIO registers enable access and control of the General-Purpose I/O port. The
General-Purpose I/O port provides a byte-wide general purpose set of signals that are individually
direction programmable.
The GPIO register accesses the data port on pins 53–60 (G[7:0]) with Data0 accessing GP[0], and
so on. The corresponding bit in the GPDIR controls the direction of the associated signal; a logic
‘1’ programs the signal as output, and a logic ‘0’ programs it as input.
When writing to the GPIO register, ‘1’s and ‘0’s are reflected in their true states on the pins that are
programmed as outputs. When reading from the GPIO register, bits programmed as inputs reflect
the true state of the signal condition on those bits; bits programmed as output will reflect the
previously set state.
Parallel Interrupt Register
The PIR indicates the source of service requests being presented by the parallel channel, either
from the parallel port or from the pipeline.
Data6
PPort
Bit 6
Bit 6
Bit 6
Dir6
Pipeline
Data5
Bit 5
Dir5
Bit 5
Bit 5
Data4
Bit 4
Bit 4
Bit 4
Dir4
0
Data3
Bit 3
Bit 3
Bit 3
Dir3
0
Data2
Bit 2
Bit 2
Bit 2
Dir2
0
Data1
Bit 1
Dir1
Bit 1
Bit 1
8-Bit Hex Address: 71
8-Bit Hex Address: 70
8-Bit Hex Address: 61
0
Default Value: 00
Default Value: 00
Default Value: 00
Datasheet
Data0
Bit 0
Dir0
Bit 0
Bit 0
0