SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 29

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

Figure 5. Interrupt Generation Logic (Continued)
Datasheet
(PCISR[5])
A1284 signal transition
from low-to-high, and
A1284(ODR[3]) = 1
A1284 signal transi-
tion from high-to-low,
and
A1284(ZDR[3]) = 1
Host has reversed the direction of the interface from ECP-forward to
ECP-reverse by driving nReverseRequest (nInit) signal low.
Host has changed the direction of the interface from ECP-reverse to ECP-
forward by driving nReverseRequest (nInit) signal high.
NegCh
(PCISR[4])
SigCh
nInit signal transition
from low-to-high, and
nInit(ODR[2]) = 1
nInit signal transition
from high to low, and
nInit(ZDR[2]) = 1
(PCISR[3])
EPPAW
(PCISR[2])
DirCh
HstBsy signal transition
from low-to-high, and
HstBsy(ODR[1]) = 1
HstBsy signal transi-
tion from high-to-low,
and
HstBsy(ZDR[1]) = 1
(PCISR[1])
IDReq
(PCISR[0])
nInit
IEEE 1284-Compatible Parallel Interface — CD1283
HstClk signal transition
from low-to-high, and
HstClk(ODR[0]) = 1
HstClk signal transition
from high-to-low, and
HstClk(ZDR[0]) = 1
In Compatibility mode, the host
has requested the peripheral to
re-initialize itself (nInit went
low).
EPP address received
on parallel port
NOTE: Interface must be in Compatibility mode when
EPPAW
(PCIER[3])
nInit
(PCIER[0])
ManMd
(PCR[7])
SigCh
(PCIER[4])
INTEN
(PFCR[4])
ManMd (PCR[7]) is set or ManMd has no affect
SigCh
(PCISR[4])
EPPAW
(PCISR[3])
DirCh
(PCISR[2])
nInit
(PCISR[0])
PPort
(PIR[6])
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