SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 71

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

7.4.8
7.4.9
7.4.10
Datasheet
Register Name: PCIER
Register Description: Parallel Channel Interrupt Enable
Access: R/W
Register Name: PCISR
Register Description: Parallel Channel Interrupt Status
Access: R/W
Register Name: PCR
Register Description: Parallel Configuration
Access: R/W
ManMd
Bit 7
Bit 7
Bit 7
0
0
Bit
7
6
5
4
3
2
1
0
Parallel Channel Interrupt Enable Register
Parallel Channel Interrupt Status Register
The PCIER and PCISR provide control and status of interrupts generated by the parallel channel
control state machine. They have the same bit definitions. Each bit in the PCIER enables the
interrupt of the same type in the PCISR. A write of any value to the PCISR in response to an
interrupt request, causes it to clear and the interrupt request to be removed.
Parallel Configuration Register
Reserved: This read-only bit is always ‘0’.
TimEn/TimOvr: Used for factory test purposes only.
NegCh: The state of this bit indicates that a change occurred in the negotiation status of the port. The NSR
indicates the new status of the parallel port.
SigCh: This bit instructs the parallel port to generate an interrupt when any of the signals specified by the
ZDR or ODR change state as programmed.
EPPAW: The state of this bit indicates that the remote master has written an EPP address to the CD1283.
The new EPP address value is placed in the EAR.
DirCh: This bit indicates that the host-side parallel port changed the direction of the interface. Generally, this
is in response to a request made by the CD1283 through the RevRq bit in the SCR (bit 0). DirCh indicates that
the direction was reversed through the defined protocol and the CD1283 can now send data to the master.
This bit is only valid in ECP and EPP (bidirectional) modes.
IDReq: The state of this bit indicates that the host has requested that the CD1283 send its ID data string. The
peripheral host should send the appropriate ID string (this is application-dependent).
nINIT: This interrupt is generated when an nINIT pulse is received in Compatibility mode. The interrupt occurs
on the leading edge of the nINIT pulse.
TimOvr
E1284
TimEn
Bit 6
Bit 6
Bit 6
NegCh
NegCh
ETxfr
Bit 5
Bit 5
Bit 5
Ig_SEL
SigCh
SigCh
Bit 4
Bit 4
Bit 4
IEEE 1284-Compatible Parallel Interface — CD1283
HTmrTst[1]
Description
EPPAW
EPPAW
Bit 3
Bit 3
Bit 3
HTmrTst[0]
DirCh
DirCh
Bit 2
Bit 2
Bit 2
MMDir
IDReq
IDReq
Bit 1
Bit 1
Bit 1
8-Bit Hex Address: 22
8-Bit Hex Address: 23
8-Bit Hex Address: 20
Default Value: 00
Default Value: 00
Default Value: 00
ManOE
nINIT
nINIT
Bit 0
Bit 0
Bit 0
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