SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 84

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

CD1283 — IEEE 1284-Compatible Parallel Interface
8.3.2
84
DMAREQ*
DMAACK*
DB[15:0]
DMAREQ*
DMAACK*
DB[15:0]
NOTE: This
NOTE: The data is sampled on the third rising edge of CLK following the assertion of DMAACK*. If DMAACK* is held
Figure 24. Asynchronous DMA Write Cycle Timing
Figure 25. Asynchronous DMA Write Cycle Timing
CLK
CLK
active for more than three CLK cycles then the next DMA write cycle will simply be delayed, but the data will
still be sampled on the third rising CLK edge following the assertion of DMAACK*. If DMAACK* is active for
CLKs, the n the data is still sampled on the third rising CLK edge following the assertion of DMAACK*
(provided that DMAACK* is active long enough for the device to lastch it. Due to this somewhat synchronous
behavior, care must be taken to guarantee that the data is valid at this CLK edge. Do not assume that the data
will be sampled on the deassertion of DMAACK*.
Figure 24
Synchronous Timing
Use the following table as a reference to timing parameters of figures in this section.
is still valid, however,
DMAACK* SYNCHRONIZED
HERE
t
t
30
t
31
19
t
Figure 25
24
DMAACK* LATCHED
HERE
t
illustrates a more robust timing.
32
SEE NOTE
DATA SAMPLED
VALID
HERE
DMAACK* SYNCHRONIZED
t
28
MAY CHANGE
HERE
t
29
t
t
30
31
t
21
VALID
DATA SAMPLED
VALID
t
32
HERE
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