EMC6D100-DK SMSC [SMSC Corporation], EMC6D100-DK Datasheet
EMC6D100-DK
Related parts for EMC6D100-DK
EMC6D100-DK Summary of contents
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... PC or embedded system. The EMC6D101, available in a 24-pin SSOP package, and the EMC6D100, available in a 28-pin SSOP package, are designed to be register compatible. The EMC6D100 offers all the features of the EMC6D101 plus additional voltage monitoring and system control features ...
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... CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC EMC6D100/EMC6D101 Page 2 DATASHEET Environmental Monitoring and Control Device Datasheet Rev ...
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... Pin SSOP Outline, 0.150” Wide Body, 0.025” Pitch 9 General Description 10 EMC6D101 SMSC EMC6D100/EMC6D101 CORRECTION Note added advising of replacement of EMC6D101 with recommended device for new designs. Vcc Supply Current, max sleep mode changed from 300 to 500 Updated temperature conversion values: changed 2 ...
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... Table of Contents EMC6D100/101 REVISIONS ........................................................................................................................ 3 CHAPTER 1 GENERAL DESCRIPTION................................................................................................. 9 CHAPTER 2 PIN CONFIGURATIONS .................................................................................................. 10 2.1 EMC6D101..................................................................................................................................... 10 2.2 EMC6D100..................................................................................................................................... 11 CHAPTER 3 RECOMMENDED IMPLEMENTATION............................................................................ 12 CHAPTER 4 PIN DESCRIPTION........................................................................................................... 14 4.1 3. PERATION OLERANCE CHAPTER 5 SMBUS INTERFACE........................................................................................................ 16 5 .............................................................................................................................. 16 LAVE DDRESS 5.2 SMB LAVE NTERFACE 5 ............................................................................................................................. 17 US ROTOCOLS 5.3.1 Byte Protocols.......................................................................................................................... 17 5 NVALID ...
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... EGISTER H AN EMP 8. TACH_PWM R EGISTER H 8. EGISTER H YNC ULSE 8.34.1 Bit [4] ON .............................................................................................................................. 66 8.35 R 86- EGISTERS H MOOTH SMSC EMC6D100/EMC6D101 R ............................................................................................. 29 EGISTERS ............................................................................................................. 30 PWM ............................................................................................ 36 S .............................................................................................................. 36 R ............................................................................................ 40 EGISTER R ........................................................................................... 40 EGISTERS : V R .............................................................................. 40 H OLTAGE EADING R ................................................................................... 41 EADING R .............................................................................. 42 ACHOMETER EADING PWM D ....................................................................................... 42 UTY ID ........................................................................................................... 44 ...
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... ....................................................................................................................... NTERFACE CHAPTER 11 PACKAGE OUTLINES .................................................................................................... 73 11 SSOP P IN ACKAGE 11 SSOP P IN ACKAGE CHAPTER 12 APPENDIX B – ADC VOLTAGE CONVERSION............................................................ 75 SMSC EMC6D100/EMC6D101 .................................................................................................. 67 EST R ................................................................................... 67 EGISTER R ............................................................................... 67 PUT TEST EGISTER R ................................................................................... 67 EGISTER R ............................................................................... 67 PUT TEST EGISTER ..................................................................................................... 68 ATINGS O , 0.150” 0.025” P ...
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... FIGURE 7.2 - AUTOMATIC FAN CONTROL...............................................................................................................34 FIGURE 7.3 - FAN TACHOMETER INPUT AND CLOCK SOURCE ...........................................................................35 FIGURE 8.1 - FAN ACTIVITY ABOVE FAN TEMP LIMIT............................................................................................53 FIGURE 8.2 - WHAT EMC6D100/EMC6D101 SEES WITH AND WITHOUT SPIKE SMOOTHING............................55 FIGURE 10.1 - PWMX OUTPUT TIMING, SYNC_MSK=0 ..........................................................................................71 FIGURE 10.2 - PWMX OUTPUT TIMING, SYNC_MSK=1 ..........................................................................................71 FIGURE 10.3 – SmBus TIMING...................................................................................................................................72 ...
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... Table 8.12 - PWM Duty vs. Register Setting ................................................................................................................56 Table 8.13 - Temperature Limit vs. Register Setting ....................................................................................................57 Table 8.14 - Absolute Limit vs. Register Setting ..........................................................................................................58 Table 8.15 - Hysteresis Settings ..................................................................................................................................59 Table 10.1 - Timing for PWM[1:3] outputs....................................................................................................................71 Table 12.1 − Analog-to-Digital Voltage Conversions for Hardware Monitoring Block...................................................75 SMSC EMC6D100/EMC6D101 Page 8 DATASHEET Environmental Monitoring and Control Device Datasheet Rev. 09-09-04 ...
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... PWM’s to drive the required fan speed. The EMC6D100 has an interrupt pin (INT#), which may be used to interrupt the host on out-of-limit temperature or voltage condition enabling an ACPI response as opposed to the host software continuously monitoring status. In auto “ ...
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... Chapter 2 Pin Configurations The Environmental Monitoring and Control device (EMC) is offered in two packages: the EMC6D101, which pin SSOP, and the EMC6D100, which pin SSOP. 2.1 EMC6D101 The EMC6D101 pin SSOP. SDA 1 2 SCL 3 GND 4 VCC 5 VID0 6 VID1 7 VID2 8 VID3 ...
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... Environmental Monitoring and Control Device Datasheet 2.2 EMC6D100 The EMC6D100 pin SSOP. The functions that this chip supports in addition to the EMC6D101 are listed below. Additional Features offered in EMC6D100: Voltage monitoring for +3.3V, +1.5V, +1.8V inputs Interrupt pin SDAT SCLK VSS VCC VID0 VID1 VID2 ...
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... FIGURE 3.1 shows how the part can be used to control additional fans by connecting two fans to one PWM output. 3.3V 1k PWM3 2.2k FIGURE 3.1 - FAN DRIVE CIRCUITRY (APPLY TO PWM DRIVING TWO FANS) 3.3V PWMx FIGURE 3.2 - FAN DRIVE CIRCUITRY (APPLY TO PWM DRIVING ONE FAN) SMSC EMC6D100/EMC6D101 3.3V MMBT3904 10 MMBT2222 10 MMBT2222 470 0 MMBT2222 ...
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... FIGURE 3.3 - FAN TACHOMETER CIRCUITRY (APPLY TO EACH FAN) MMBT3904 2 XSTR 1 3 FIGURE 3.4 - REMOTE DIODE (APPLY TO REMOTE2 LINES) Notes: 100pf cap is optional and should be placed close to the EMC6D100/EMC6D101 if used. The voltage at PWM3 must be at least 2.0V to avoid triggering Address Enable. SMSC EMC6D100/EMC6D101 12V 10k TACH Input 10k 4 ...
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... Vccp 23 +12V 21 +1.5V - (note 1) +1.8V - (note 1) +3.3V - (note 1) SMSC EMC6D100/EMC6D101 PIN TYPE (EMC6D100) 1 Digital I/O System Management Bus Data. Open-drain output. 5V tolerant. SMBus 2.0 compliant. (Open Drain) 2 Digital I/O System Management Bus Clock. Open-drain output. 5V tolerant. SMBus 2.0 Compliant. (Open Drain) 5 Digital Input Voltage processor. This value is read in the VID0- VID4 Status Register ...
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... Note 1: These pins are in EMC6D100 only. 4.1 3.3V Operation, 5V Tolerance The EMC6D100/EMC6D101 is intended to operate with a nominal 3.3V power supply. The analog voltage pins are connected to voltage sources at their respective nominal levels. All digital signal pins are 3V switching but are tolerant to 5V. SMSC EMC6D100/EMC6D101 PIN ...
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... EMC6D100/EMC6D101 address. This feature eliminates the possibility of a glitch on the SMBus interfering with address selection. ADDRESS SELECT this way, there can three EMC6D100/EMC6D101 devices on the SMBus at any time. Multiple EMC6D100/EMC6D101 devices can be used to monitor additional processors and temperature zones. Start 0 SDA SCL FIGURE 5 ...
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... Read Byte The Read Byte protocol is used to read data from the registers. The data will only be read if the protocol shown in Table 5.2 is performed correctly. Only one byte is transferred at time for a Read Byte protocol. SMSC EMC6D100/EMC6D101 Table 5.1 -SMBus Write Byte Protocol WR ACK REG. ADDR ACK ...
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... The only valid protocols are the Write Byte, Read Byte, Send Byte, and Receive Byte protocols, which are described above. The EMC6D100/EMC6D101 device responds to three SMBus slave addresses: 1) The SMBus slave address that supports the valid protocols defined in the previous sections is determined by the level on the Address Select and Address Enable pins as shown in section 5 ...
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... SMBus Alert Response Address EMC6D100: The EMC6D100 device implements the SMBALERT# signal. The INT# interrupt pin can be used as the SMBALERT#. SMBALERT# is used in conjunction with the SMBus General Call Address, 0001 100. In order for the INT# signal to become active and for the device to respond to the Alert Response address, the INTEN bit (register 7Ch bit 2) must be set and the event must be properly enabled onto the INT# pin ...
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... Address and respond with its device address. The host performs a modified Receive Byte operation with the alert response address. The 7-bit device address provided by the EMC6D100/EMC6D101 device is placed in the 7 most significant bits of the byte. The eighth bit can be a zero or one. ...
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... Input Monitoring The EMC6D100/EMC6D101 Device’s monitoring function is started by writing a ‘1’ to the START bit in the Ready/Lock/Start Register (0x40). Measured values from the analog inputs and temperature sensors are stored in Reading Registers. The values in the reading registers can be accessed via the SMBus interface. ...
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... CYCLE MONITORING MODE In cycle monitoring mode, the part completes all sampling and conversions, then waits to repeat the process. It repeats the sampling and conversion process every second (1.4 sec max). The sampling and SMSC EMC6D100/EMC6D101 REGISTER 1 Remote Diode Temp Reading 1 2 Ambient Temperature reading ...
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... See the description of the Interrupt Status registers in section Chapter 8 Register Set. Each interrupt event can be enabled into the interrupt status registers. See the figure below for the status and enable bits used to control the interrupt bits and INT# pin. SMSC EMC6D100/EMC6D101 Page 23 DATASHEET ...
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... DIODE FAULT The EMC6D100/EMC6D101 Chip automatically sets the associated diode fault bit to 1 when there is either a short or open circuit fault on the Remote x+ or Remote x- thermal diode input pins. The occurrence of a fault will cause 80h to be loaded into the associated reading register, which will cause the corresponding zone error bit to be set ...
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... This is a low power mode in which bias currents are ‘on’ but the Hardware Monitor Block is not operating. In this mode, the A/D converter and monitoring cycle will be turned off. Serial bus communication is still possible with any register in the Hardware Monitor Block while in this low-power mode. SMSC EMC6D100/EMC6D101 Page 25 DATASHEET ...
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... Analog Voltage Measurement EMC6D101 monitors power supplies +2.5V, +5V, +12V, Vccp, and VCC EMC6D100 monitors additional power supplies +3.3V, +1.5V, +1.8V The Hardware Monitor Block contains inputs for directly monitoring the power supplies (+ +3.3V, +2.5V, +1.8V, +1.5V, +Vccp and VCC). These inputs are scaled internally to a internal reference ...
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... C … 0 -50 C … 0 -25 C … … 0 +25 C … 0 +50 C … SMSC EMC6D100/EMC6D101 0 C. READING (DEC) READING (HEX) -127 81h … … -50 CEh … … -25 E7h … … -1 FFh 0 00h 1 01h … … 25 19h … … 50 32h … ...
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... The part implements temperature “spike” smoothing to prevent the fan from spinning up rapidly as a result of a spike in temperature. The spike smoothing registers allow the smoothing interval to be selected for each zone. See the description of registers 62h and 63h. SMSC EMC6D100/EMC6D101 READING (DEC) READING (HEX) ...
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... The following sections describe the various fan control and monitoring modes in the part. 7.1 General Description The EMC6D100/EMC6D101 device is capable of driving three DC fans and monitoring up to four fans with tachometer outputs in either Manual Fan Control mode or in Auto Fan Control mode. The fan outputs (PWMx pins) are controlled by a Pulse Width Modulation (PWM) scheme. ...
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... If an out-of-limit condition occurs, the corresponding status bit will be set in the Interrupt Status registers. Setting this status bit will generate an interrupt signal on the INT# pin (if enabled – EMC6D100 only). Software must handle the interrupt condition and modify the operation of the EMC6D100/EMC6D101 accordingly ...
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... AUTO FAN CONTROL OPERATING MODE The EMC6D100/EMC6D101 chip implements automatic fan control. In Auto Fan Mode, the chip automatically adjusts the PWM duty cycle of the PWM outputs, according to the flow chart below. PWM outputs are assigned to a thermal zone based on the fan configuration registers possible to have more than one PWM output assigned to a thermal zone ...
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... Set the hysteresis value for the minimum temperature that will turn the fans off. This value will hold the fans on until the temperature goes a certain amount below the value programmed in the Zone x Temp Limit registers. This value will prevent the fan from oscillating between on and off if the SMSC EMC6D100/EMC6D101 Auto Fan Mode Initiated ...
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... Provided that the fan has adequate cooling capacity for all environmental and power dissipation conditions, this system will maintain the temperature within acceptable limits, while allowing the fan to run slower (and quieter) when less cooling is required. SMSC EMC6D100/EMC6D101 It can also monitor current temperature readings through the Page 33 DATASHEET Rev ...
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... PWM must be in the valid range for spin-up to end. 2. The tachometer reading register always gives the actual reading of the tachometer input interrupt bits are set during spin-up. SMSC EMC6D100/EMC6D101 Spin Up MIN Hysteresis Temperature This causes spin-up to continue until the ...
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... These registers are updated at least once every second. The frequency of the clock source for the tachometer logic is 90kHz. This register is latched on the rising edge of every other fan tachometer pulse and when the fan count reaches FFFFh. This latter condition is the stalled fan event. SMSC EMC6D100/EMC6D101 T R ...
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... The status bit for a fan failure is set when the tach reading is above the value set in the tach minimum register. This interrupt status bit cannot be cleared by reading the status register as long as the count value is above the minimum. The tachometer can generate an INT# if properly enabled (EMC6D100 only). 7.5.3 FAN INTERRUPT STATUS BITS The status bits for the fan events are in Interrupt Status Register 2 (42h) ...
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... Interrupt Status Register 2 43h R VID0-4 44h R/W 2.5V Low Limit 45h R/W 2.5V High Limit 46h R/W Vccp Low Limit 47h R/W Vccp High Limit 48h R/W VCC Low Limit 49h R/W VCC High Limit SMSC EMC6D100/EMC6D101 Bit 7 Abbr. (MSb) Bit 6 Bit 5 Bit 4 Bit 3 SMSC OF2R ...
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... R/W Zone 1 Fan Temp Limit 68h R/W Zone 2 Fan Temp Limit 69h R/W Zone 3 Fan Temp Limit Zone 1 Temp Absolute 6Ah R/W Limit Zone 2 Temp Absolute 6Bh R/W Limit Zone 3 Temp Absolute 6Ch R/W Limit SMSC EMC6D100/EMC6D101 Bit 7 Abbr. (MSb) Bit 6 Bit 5 Bit 4 Bit 3 V50L V50H ...
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... In this case, the register is writeable when the start bit is set, but not when the lock bit is set. 2. The Lock and Start bits in the Ready/Lock/Start register are locked by the Lock Bit. The OVRID bit is always writeable, both when the start bit is set and when the lock bit is set. SMSC EMC6D100/EMC6D101 Bit 7 Abbr. (MSb) Bit 6 ...
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... It may be switched to the internal channel by setting bit 4 of the Special Function Register to 1. 8.4 Registers 20-24h, 70-72h: Voltage Reading REGISTER READ/ REGISTER ADDRESS WRITE NAME 20h R 2.5V 21h R Vccp SMSC EMC6D100/EMC6D101 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 (MSB BIT 7 BIT 6 BIT 5 ...
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... The Temperature Reading registers will be updated automatically by the EMC6D100/EMC6D101 Chip with a minimum frequency of 4Hz. These registers are read only – a write to these registers has no effect. ...
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... These registers are read only – a write to these registers has no effect. 8.7 Registers 30-32h: Current PWM Duty REGISTER READ/ REGISTER ADDRESS WRITE NAME 1 30h R/W Fan1 Current SMSC EMC6D100/EMC6D101 READING (DEC) READING (HEX) -127 81h -50 CEh 0 00h 50 32h 127 7Fh 80h ...
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... Lock bit is set. Any further attempts to write to these registers shall have no effect. The Current PWM Duty registers store the duty cycle that the EMC6D100/EMC6D101 Chip is currently driving the PWM signals at. At initial power-on, the duty cycle is 100% and thus, when read, this register will return FFh ...
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... The four least significant bits of the Version / Stepping register [3:0] contain the current stepping of the EMC6D100/EMC6D101 silicon. The four most significant bits [7:4] reflect the EMC6D100/EMC6D101 version number. The EMC6D100/EMC6D101 has a fixed version number of 0110b. For the A0 stepping of EMC6D100/EMC6D101, EMC6D100/EMC6D101, this register will read 01100001b. ...
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... This register bit becomes read only once it is set. The EMC6D100/EMC6D101 sets this bit automatically after the part is fully powered up, has completed the power-up-reset process, and after all A/D converters are functioning (all bias conditions for the A/Ds have stabilized and the A/Ds are in operational mode). (Always reads back ‘ ...
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... Interrupt Status Register (or both). Therefore, S/W can poll this register, and only if bit 7 is set do the other registers need to be read. This bit is cleared (set to 0) automatically by the EMC6D100/EMC6D101 if there are no bits set in Interrupt Status Registers 2 and 3. This register is read only – a write to this register has no effect. ...
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... The Interrupt Status Register 2 register holds a set bit until the event is read by software. The contents of this register are cleared (set to 0) automatically by the EMC6D100/EMC6D101 after it is read by software, if the voltage or temperature no longer violates the limits set in the limit and parameter registers the fan reading register is no longer above the minimum ...
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... This register holds a set bit until the event is read by software. The contents of this register is cleared (set to 0) automatically by the EMC6D100 after it is read by software, if the voltage no longer violates the limit set in the limit and parameter register. Once set, the Interrupt Status Register 3 bits remain set until a read event occurs, even if the voltage or temperature no longer violates the limits set in the limit and parameter registers ...
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... VOLTAGE 1.5V 1.5V C0h 1.8V 1.8V C0h 2.5V 2.5V C0h Vccp 2.25V C0h VCC 3.3V C0h 3.3V 3.3V C0h 5V 5.0V C0h 12V 12.0V C0h Note: The voltages 1.5V, 1.8V and 3.3V in the table above are applicable to the EMC6D100 only. SMSC EMC6D100/EMC6D101 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 (MSB ...
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... EMC6D100/EMC6D101 in the Interrupt Status Register 1 (41h). For example, if the temperature read from the Remote1- and Remote2+ inputs exceeds the Processor (Zone1) High Temp register limit setting, Interrupt Status Register 1 ZN1 bit will be set. The temperature limits in these registers are represented as 8 bit, 2’ ...
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... Fan Mode, the fan will be assigned to a zone, and its PWM duty cycle will be adjusted according to the temperature of that zone. If ‘Hottest’ option is selected (101 or 110), the fan will be controlled by the hottest of zones 2 and zones 1, 2, and 3. If one of these options is selected, the fan is controlled by the SMSC EMC6D100/EMC6D101 BIT 7 BIT 6 ...
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... Configuration register (7Fh). If disabled, the all fans go on full for the duration of their associated spin up time. Note that the Tachx minimum registers must be programmed to a value less than FFFFh in order for the spin up reduction to work properly. SMSC EMC6D100/EMC6D101 Table 8.6 - Fan Zone Setting FAN CONFIGURATION ...
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... Below Fan Temp Limit: Fan is off or at Fan PWM Minimum depending on bit[7:5] of register 62h and bit 2 of register 7Fh Temperature FIGURE 8.1 - FAN ACTIVITY ABOVE FAN TEMP LIMIT SMSC EMC6D100/EMC6D101 Table 8.7 - Fan Spin-Up Register SPIN UP SPIN[2:0] TIME 000 ...
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... FREQ[2:0] Table 8.9 - Register Setting vs. Temperature Range RAN[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SMSC EMC6D100/EMC6D101 PWM FREQUENCY 000 11.0 Hz 001 14.6 Hz 010 21.9 Hz 011 29.3 Hz 100 35.2 Hz 101 44.0 Hz 110 58.6 Hz 111 87.7 Hz Range Selection (Default =1100=32°C) RANGE (° ...
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... ZN1-2, ZN1-1, and ZN1-0 control smoothing time for Zone 1 ZN2-2, ZN2-1, and ZN2-0 control smoothing time for Zone 2 ZN3-2, ZN3-1, and ZN3-0 control smoothing time for Zone 3 Temperature spike with spike smoothing disabled FIGURE 8.2 - WHAT EMC6D100/EMC6D101 SEES WITH AND WITHOUT SPIKE SMOOTHING SMSC EMC6D100/EMC6D101 BIT 7 BIT 6 BIT 5 ...
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... These registers specify the minimum duty cycle that the PWM will output when the measured temperature reaches the Temperature LIMIT register setting. Table 8.12 - PWM Duty vs. Register Setting MINIMUM PWM DUTY 0% 25% 50% 100% SMSC EMC6D100/EMC6D101 Table 8.10 - Spike Smoothing SPIKE SMOOTHED OVER (SEC) 35 17.6 11.8 7.0 4.4 3.0 1 ...
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... In Auto Fan mode, if any zone exceeds the temperature set in the Absolute limit register, all PWM outputs will increase their duty cycle to 100% except those that are disabled via the fan configuration registers. This is a safety feature that attempts to cool the system if there is a potentially catastrophic thermal event. SMSC EMC6D100/EMC6D101 BIT 7 BIT 6 ...
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... The fan will remain on, at Fan PWM Minimum, until the temperature goes a certain amount below Fan Temp Limit. That is, when the temperature is less than the temperature limit minus the hysteresis value, the fan will turn off. The Hysteresis registers control this amount. See below table for details. SMSC EMC6D100/EMC6D101 ABS LIMIT (DEC) ABS LIMIT (HEX) -127 ...
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... Bit[0] Selects the ADC test mode. The default for this bit is zero, which deactivates ADC test mode. Bit[1] Selects the digital test mode. The default for this bit is zero, which deactivates digital test mode. SMSC EMC6D100/EMC6D101 Table 8.15 - Hysteresis Settings SETTING HYSTERESIS 0h 0° ...
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... Monitoring Interface” section, the Internal Address register should be set up with a valid address location by either a send byte protocol or a write byte protocol after power-on-reset, before the receive byte protocol. Bit[4] Indicates an invalid slave address was detected. SMSC EMC6D100/EMC6D101 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 ...
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... This register contains the following bits: Bit[0] Low-Power Mode Select 0= Sleep Mode (default) 1= Shutdown Mode Bit[1] Monitoring Mode Select 0= Continuous Monitor Mode (default) 1= Cycle Monitor Mode Bit[2] nINT Enable (EMC6D100 only) SMSC EMC6D100/EMC6D101 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 (MSB ...
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... Bit[3] nINT Voltage Enable (EMC6D100 only) 0=Out-of-limit voltages do not affect the state of the nINT pin (default) 1=Enable out-of-limit voltages to make the nINT pin active low Bit [4] Offset Register Configure 0= offset register configured to the external temperature channel ...
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... Configuration These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. This register contains the following bits: Bit[1] INT# pin enable: 0=INT# disabled, 1=INT# enabled (EMC6D100 only) SMSC EMC6D100/EMC6D101 BIT 7 BIT 6 BIT 5 ...
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... TEMP enable bit that enables temperature events to the INT# pin. This register contains the following bits: Bit[0] Fan Interrupt Enable Bit[1] Fan 1 Event Enable Bit[2] Fan 2 Event Enable Bit[3] Fan 3 Event Enable SMSC EMC6D100/EMC6D101 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 (MSB) RES AMB TEMP ...
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... Bits[3:2] Tach2. These bits determine the PWM associated with this Tach. See bit combinations below. Bits[5:4] Tach3. These bits determine the PWM associated with this Tach. See bit combinations below. Bits[7:6] Tach4. These bits determine the PWM associated with this Tach. See bit combinations below. SMSC EMC6D100/EMC6D101 BIT 7 BIT 6 ...
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... Smoothed temperatures are represented as 8 bit, 2’s complement, signed numbers in Celsius, as shown in Table 8.2 - Temperature vs. Register Reading. These registers are read only – a write to these registers has no effect. These registers hold appropriate values whether smoothing is enabled or not. SMSC EMC6D100/EMC6D101 BITS[1:0], BITS[3:2], PWM ASSOCIATED BITS[5:4], BITS[7:6] ...
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... R/W Reg 1 This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no effect. This register must not be written. Writing this register may produce unexpected results. SMSC EMC6D100/EMC6D101 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 (MSB) ...
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... A PARAMETER SYMBOL V Supply Current CC Active Mode Sleep Mode Shutdown Mode Temperature-to-Digital Converter Characteristics Internal Temperature Accuracy External Diode Sensor Accuracy Remote Source Current High Level Low Level SMSC EMC6D100/EMC6D101 MIN TYP MAX 500 ±1 ...
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... SDA, PWM1, PWM2, PWM3/ADDRESS ENABLE, INT#) Low Input Level High Input Level Hysteresis Low Output Level Leakage Current (ALL - Digital) Input High Current ILEAK Input Low Current ILEAK Digital Input Capacitance SMSC EMC6D100/EMC6D101 MIN TYP MAX TUE ±2 DNL ±1 PSS ±1 t 1.0 1.4 C(Cycle) t ...
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... It is 78ms (typical) for option measurements are averaged for the remote diode temperature reading and a single measurement is taken for all voltage and the internal temperature reading (i.e., no averaging). Note 4: All leakage currents are measured with all pins in high impedance. SMSC EMC6D100/EMC6D101 Page 70 DATASHEET Environmental Monitoring and Control Device Datasheet Rev ...
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... Note 1: This value is programmable by the PWM frequency bits located in the FRFx registers Note 2: The PWM High Time is based on a percentage of the total PWM period (min=0/256*T =255/256*T ). During Spin-up the PWM High Time can reach a 100% or Full On. (T PWM SMSC EMC6D100/EMC6D101 ...
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... Note 2: At 400kHz, spikes of a maximum pulse width of 50ns must be suppressed by the input filter. Note 3: If using 100 kHz clock frequency, the next data bit output to the SDA line will be 1250 ns (1000 ns (T max) + 250 SMSC EMC6D100/EMC6D101 SU;STA t ...
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... Dimension for foot length L measured at the gauge plane 0.010 inches above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC EMC6D100/EMC6D101 MAX REMARKS 0.069 Overall Package Height ...
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... Dimension for foot length L measured at the gauge plane 0.010 inches above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC EMC6D100/EMC6D101 MAX 0.069 Overall Package Height 0.010 0.061 Body Thickness 0 ...
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... SMSC EMC6D100/EMC6D101 Input Voltage 2 <0.013 <0.009 0.013–0.026 0.009-0.019 0.008-0.016 0.026– ...