EMC6D100-DK SMSC [SMSC Corporation], EMC6D100-DK Datasheet - Page 20

• Manufacturer Part Number: EMC6D100-DK
• Description: ENVIRONMENTAL MONITORING AND CONTROL DEVICE WITH AUTOMATIC FAN CAPABILITY
• Manufacturer: SMSC [SMSC Corporation]

Environmental Monitoring and Control Device
Datasheet
enabled onto the INT# pin via the enable bits for each type of event (i.e., temperature, voltage and fan).
See the “INTERRUPT STATUS REGISTER” section.
The device can signal the host that it wants to talk by pulling the SMBALERT# low, if a status bit is set in
one of the interrupt status registers and properly enabled onto the INT# pin. The host processes the
interrupt and simultaneously accesses all SMBALERT# devices through a modified Receive Byte
operation with the Alert Response Address (ARA).
The EMC6D100/EMC6D101 Device, which pulled SMBALERT# low, will acknowledge the Alert Response
Address and respond with its device address.
The host performs a modified Receive Byte operation with the alert response address. The 7-bit device
address provided by the EMC6D100/EMC6D101 device is placed in the 7 most significant bits of the byte.
The eighth bit can be a zero or one.
Table 5.5 - Modified SMBus Receive Byte Protocol Response to ARA
ALERT
EMC6D100/EMC6D101
FIELD:
START
RESPONSE
RD
ACK
NACK
STOP
SLAVE ADDRESS
ADDRESS
BITS:
1
7
1
1
8
1
1
After acknowledging the slave address, the EMC6D100/EMC6D101 device will disengage the
SMBALERT# pulldown by clearing the INT enable bit. If the condition that caused the interrupt remains,
the Fan Control device will reassert the SMBALERT# on the next monitoring cycle, provided the INT
enable bit has been set back to ‘1’ by software.
EMC6D101:
The EMC6D101 part does not have an interrupt pin. This part does not normally acknowledge or respond
to the Alert Response Address. However, the Device will respond as described above if the INTEN bit
(register 7Ch bit 2) is set, and if a status bit is set in one of the interrupt status registers and is properly
enabled onto the INT# signal. Each interrupt event must be enabled into the interrupt status registers, and
the status bits must be enabled onto the INT# signal via the enable bits for each type of event (i.e.,
temperature, voltage and fan). See the “INTERRUPT STATUS REGISTER” section.
SMSC EMC6D100/EMC6D101
Page 20
Rev. 09-09-04
DATASHEET