AD9653BCPZ-125 Analog Devices, AD9653BCPZ-125 Datasheet - Page 25

• Manufacturer Part Number: AD9653BCPZ-125
• Description: the ad9653 is a quad, 16-bit, 125 msps analog-to-digital converter (adc) with an...
• Manufacturer: Analog Devices

Data Sheet
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 50). The internal buffer generates the
positive and negative full-scale references for the ADC core.
It is not recommended to leave the SENSE pin floating.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the
inputs, CLK+ and CLK−, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased internally
(see Figure 44) and require no external bias.
Clock Input Options
The
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regard-
less of the type of signal being used, clock source jitter is of the
most concern, as described in the Jitter Considerations section.
Figure 62 and Figure 63 show two preferred methods for clock-
ing the
divider). A low jitter clock source is converted from a single-
ended signal to a differential signal using either an RF transformer
or an RF balun.
AD9653
–10
–15
10
–5
AD9653
–2
–4
–6
–8
5
0
–40
4
2
0
–40
has a flexible clock input structure. The clock input
–20
(at clock rates up to 1 GHz prior to internal clock
Figure 60. Typical V
Figure 61. Typical V
–15
0
TEMPERATURE (°C)
TEMPERATURE (°C)
10
20
REF
REF
= 1.0 V Drift
= 1.3 V Drift
AD9653
35
40
sample clock
60
60
80
85
Rev. 0 | Page 25 of 40
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 1 GHz, and the RF transformer is recom-
mended for clock frequencies from 20 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary winding limit clock excursions into the
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the
preserving the fast rise and fall times of the signal that are critical
to achieving low jitter performance. However, the diode capaci-
tance comes into play at frequencies above 500 MHz. Care must be
taken in choosing the appropriate signal limiting diode.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 64. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516/AD9517
excellent jitter performance.
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 65. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517
clock drivers offer excellent jitter performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 μF capacitor (see
Figure 66).
CLOCK
CLOCK
CLOCK
INPUT
INPUT
INPUT
CLOCK
INPUT
Figure 62. Transformer-Coupled Differential Clock (Up to 200 MHz)
50kΩ
Figure 63. Balun-Coupled Differential Clock (Up to 1 GHz)
Figure 64. Differential PECL Sample Clock (Up to 1 GHz)
50Ω
0.1µF
50Ω
0.1µF
0.1µF
0.1µF
0.1µF
50kΩ
100Ω
ADT1-1WT, 1:1 Z
Mini-Circuits
PECL DRIVER
0.1µF
XFMR
AD951x
240Ω
®
0.1µF
0.1µF
0.1µF
0.1µF
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
DIODES:
DIODES:
240Ω
100Ω
AD9653
0.1µF
0.1µF
clock drivers offer
CLK+
CLK–
CLK+
CLK–
AD9653
CLK+
CLK–
ADC
AD9653
while
ADC
ADC
to