AD9653BCPZ-125 Analog Devices, AD9653BCPZ-125 Datasheet - Page 35

• Manufacturer Part Number: AD9653BCPZ-125
• Description: the ad9653 is a quad, 16-bit, 125 msps analog-to-digital converter (adc) with an...
• Manufacturer: Analog Devices

Data Sheet
ADDR
(Hex)
0x0B
0x0C
0x0D
0x10
0x14
0x15
0x16
Parameter Name
Clock divide
(global)
Enhancement
control
Test mode (local
except for PN
sequence resets)
Offset adjust
(local)
Output mode
Output adjust
Output phase
Bit 7
(MSB)
Open
Open
Open
Open
(affects user input test
User input test mode
Open
11 = alternate once
10 = single once
Bits[3:0] = 1000)
01 = alternate
mode only,
00 = single
Bit 6
Open
Open
LVDS-ANSI/
LVDS-IEEE
option
0 = LVDS-
ANSI
1 = LVDS-
IEEE
reduced
range link
(global)
see
Table 20
Open
(value is number of input clock
Offset adjust in LSBs from +127 to −128 (twos complement format)
Input clock phase adjust[6:4]
cycles of phase delay)
see Table 21
Bit 5
Open
Open
Reset
PN long
gen
Open
8-bit device offset adjustment [7:0] (local)
termination[1:0]
Output driver
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
00 = none
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Bit 4
Open
Open
Reset PN
short
gen
Open
Bit 3
Open
Open
Open
Open
0100 = alternating checkerboard
Output clock phase adjust[3:0]
0111 = one/zero word toggle
Output test mode[3:0] (local)
1100 = mixed bit frequency
0101 = PN 23 sequence
0110 = PN 9 sequence
0001 = midscale short
1001 = 1-/0-bit toggle
Bit 2
Chop
mode
0 = off
1 = on
Output
invert
(local)
Open
(0000 through 1011)
1011 = one bit high
0000 = off (default)
0011 = negative FS
0010 = positive FS
1000 = user input
1010 = 1× sync
see Table 22
Clock divide ratio[2:0]
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Bit 1
Open
Open
Open
Bit 0
(LSB)
Open
Output
format
0 =
offset
binary
1 =
twos
comple-
ment
(global)
Output
drive
0 = 1×
drive
1 = 2×
drive
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x01
0x00
0x03
Comments
Enables/
disables chop
mode.
When set, the
test data is
placed on the
output pins in
place of
normal data.
Device offset
trim.
Configures
the outputs
and the
format of the
data.
Determines
LVDS or other
output
properties.
On devices
that use
global clock
divide,
determines
which phase
of the divider
output is used
to supply the
output clock.
Internal
latching is
unaffected.
AD9653