AD9653BCPZ-125 Analog Devices, AD9653BCPZ-125 Datasheet - Page 38

• Manufacturer Part Number: AD9653BCPZ-125
• Description: the ad9653 is a quad, 16-bit, 125 msps analog-to-digital converter (adc) with an...
• Manufacturer: Analog Devices

AD9653
Output Phase (Register 0x16)
Bit 7—Open
Bits[6:4]—Input Clock Phase Adjust
Table 21. Input Clock Phase Adjust Options
Input Clock Phase
Adjust, Bits[6:4]
000 (Default)
001
010
011
100
101
110
111
Bits[3:0]—Output Clock Phase Adjust
Table 22. Output Clock Phase Adjust Options
Output Clock (DCO),
Phase Adjust, Bits[3:0]
0000
0001
0010
0011 (Default)
0100
0101
0110
0111
1000
1001
1010
1011
Table 23. SPI Register Options
Register 0x21
Contents
0x30
0x20
0x10
0x00
0x34
0x24
0x14
0x04
0x40
Serial Output Number
of Bits (SONB)
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
Number of Input Clock Cycles of
Phase Delay
0
1
2
3
4
5
6
7
DCO Phase Adjustment (Degrees
Relative to D0±x/D1±x Edge)
0
60
120
180
240
300
360
420
480
540
600
660
Serialization Options Selected
Frame Mode
1×
1×
1×
1×
2×
2×
2×
2×
1×
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Serial Data Mode
DDR two-lane, bytewise
DDR two-lane, bitwise
SDR two-lane, bytewise
SDR two-lane, bitwise
DDR two-lane, bytewise
DDR two-lane, bitwise
SDR two-lane, bytewise
SDR two-lane, bitwise
DDR one-lane, wordwise
Serial Output Data Control (Register 0x21)
The serial output data control register is used to program the
AD9653
capture solution. Table 23 describes the various serialization
options available in the AD9653.
Sample Rate Override (Register 0x100)
This register is designed to allow the user to downgrade the sample
rate. Settings in this register are not initialized until Bit 0 of the
transfer register (Register 0xFF) is written high.
User I/O Control 2 (Register 0x101)
Bits[7:1]—Open
Bit 0—SDIO Pull-Down
Bit 0 can be set to disable the internal 30 kΩ pull-down on the
SDIO pin, which can be used to limit the loading when many
devices are connected to the SPI bus.
User I/O Control 3 (Register 0x102)
Bits[7:4]—Open
Bit 3—VCM Power-Down
Bit 3 can be set high to power down the internal VCM
generator. This feature is used when applying an external
reference.
Bits[2:0]—Open
in various output data modes depending upon the data
DCO Multiplier
4 × f
4 × f
8 × f
8 × f
4 × f
4 × f
8 × f
8 × f
8 × f
S
S
S
S
S
S
S
S
S
Timing Diagram
Figure 2 (default setting)
Figure 2
Figure 2
Figure 2
Figure 3
Figure 3
Figure 3
Figure 3
Figure 4
Data Sheet