AD9653BCPZ-125 Analog Devices, AD9653BCPZ-125 Datasheet - Page 32

• Manufacturer Part Number: AD9653BCPZ-125
• Description: the ad9653 is a quad, 16-bit, 125 msps analog-to-digital converter (adc) with an...
• Manufacturer: Analog Devices

AD9653
HARDWARE INTERFACE
The pins described in Table 17 comprise the physical interface
between the user programming device and the serial port of the
AD9653. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the
controller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the
tioning at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are strapped to DRVDD or ground
during device power-on, they are associated with a specific
function. Table 15 and Table 16 describe the strappable
functions supported on the AD9653.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/OLM pin, the SCLK/DTP pin, and the PDWN pin
serve as standalone CMOS-compatible control pins. When the
device is powered up, it is assumed that the user intends to use the
pins as static control lines for the output lane mode, digital test
AD9653
to prevent these signals from transi-
AN-812 Application
Note, Micro-
Rev. 0 | Page 32 of 40
pattern, and power-down feature control. In this mode, CSB
should be connected to AVDD, which disables the serial port
interface.
Note that, when the CSB pin is tied to AVDD, the
is on by default and remains on unless the part is placed in SPI
mode and controlled via the SPI. Refer to the Clock Duty Cycle
section for more information on the DCS.
When the device is in SPI mode, the PDWN pin (if enabled)
remains active. For SPI control of power-down, the PDWN pin
should be set to its default state.
SPI ACCESSIBLE FEATURES
Table 18 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the
via SPI. The
following Table 19, the external memory map register table.
Table 18. Features Accessible Using the SPI
Feature Name
Power Mode
Clock
Offset
Test I/O
Output Mode
Output Phase
AN-877 Application
AD9653
Description
Allows the user to set either power-down mode
or standby mode
Allows the user to set the clock divider, set the
clock divider phase, and enable the sync
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have
known data on output bits
Allows the user to set the output mode
Allows the user to set the output clock polarity
part-specific features are described in detail
Note, Interfacing to High Speed ADCs
Data Sheet
AD9653
DCS