PCF2129AT/2,518 NXP Semiconductors, PCF2129AT/2,518 Datasheet - Page 46

• Manufacturer Part Number: PCF2129AT/2,518
• Description: Real Time Clock
• Manufacturer: NXP Semiconductors
• Series: PCF2129r

Specifications of PCF2129AT/2,518

• Rohs: yes
• Function: Clock, Calendar, Alarm, Watchdog, Timestamp
• Rtc Bus Interface: I2C, SPI
• Date Format: Binary
• Time Format: Binary
• Supply Voltage - Max: 4.2 V
• Supply Voltage - Min: 1.2 V
• Maximum Operating Temperature: + 60 C
• Minimum Operating Temperature: - 15 C
• Mounting Style: SMD/SMT
• Package / Case: SOP-20
• Battery Backup Switching: Yes
• Factory Pack Quantity: 2000

NXP Semiconductors
PCF2129AT
Product data sheet
9.1.1 Data transmission
9.1 SPI-bus interface
Data transfer to and from the device is made by a 3 line SPI-bus (see
lines for input and output are split. The data input and output line can be connected
together to facilitate a bidirectional data bus (see
whenever the chip enable line pin SDA/CE is inactive.
Table 49.
[1]
The chip enable signal is used to identify the transmitted data. Each data transfer is a
whole byte, with the Most Significant Bit (MSB) sent first.
The transmission is controlled by the active LOW chip enable signal SDA/CE. The first
byte transmitted is the command byte. Subsequent bytes will be either data to be written
or data to be read (see
The command byte defines the address of the first register to be accessed and the
read/write mode. The address counter will auto increment after every access and will
reset to zero after the last valid register is accessed. The R/W bit defines if the following
bytes will be read or write information.
Symbol
SDA/CE
SCL
SDI
SDO
Fig 27. SDI, SDO configurations
Fig 28. Data transfer overview
The chip enable must not be wired permanently LOW.
Serial interface
Function
chip enable input;
active LOW
serial clock input
serial data input
serial data output
data bus
SDA/CE
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 12 February 2013
Figure
COMMAND
28).
[1]
two wire mode
SDO
SDI
Description
when HIGH, the interface is reset;
when SDA/CE is HIGH, input may float;
when SDA/CE is HIGH, input may float;
push-pull output;
input may be higher than V
input may be higher than V
input may be higher than V
input data is sampled on the rising edge of SCL
drives from V
output data is changed on the falling edge of SCL
DATA
Integrated RTC, TCXO and quartz crystal
single wire mode
SDO
SDI
SS
DATA
Figure
to V
001aai560
BBS
27). The SPI-bus is initialized
;
DD
DD
DD
;
PCF2129AT
DATA
Table
© NXP B.V. 2013. All rights reserved.
013aaa311
49). The data
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