PCF2129AT/2,518 NXP Semiconductors, PCF2129AT/2,518 Datasheet - Page 71

• Manufacturer Part Number: PCF2129AT/2,518
• Description: Real Time Clock
• Manufacturer: NXP Semiconductors
• Series: PCF2129r

Specifications of PCF2129AT/2,518

• Rohs: yes
• Function: Clock, Calendar, Alarm, Watchdog, Timestamp
• Rtc Bus Interface: I2C, SPI
• Date Format: Binary
• Time Format: Binary
• Supply Voltage - Max: 4.2 V
• Supply Voltage - Min: 1.2 V
• Maximum Operating Temperature: + 60 C
• Minimum Operating Temperature: - 15 C
• Mounting Style: SMD/SMT
• Package / Case: SOP-20
• Battery Backup Switching: Yes
• Factory Pack Quantity: 2000

NXP Semiconductors
25. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. Dependency between POR and oscillator . . . . . .21
Fig 11. Power-On Reset (POR) system. . . . . . . . . . . . . .21
Fig 12. Power-On Reset Override (PORO) sequence,
Fig 13. Data flow of the time function. . . . . . . . . . . . . . . .26
Fig 14. Access time for read/write operations . . . . . . . . .26
Fig 15. Alarm function block diagram. . . . . . . . . . . . . . . .27
Fig 16. Alarm flag timing diagram . . . . . . . . . . . . . . . . . .29
Fig 17. WD_CD set logic 1: watchdog activates an
Fig 18. Timestamp detection with two push-buttons on
Fig 19. Interrupt block diagram . . . . . . . . . . . . . . . . . . . .38
Fig 20. INT example for SI and MI when TI_TP is
Fig 21. INT example for SI and MI when TI_TP is
Fig 22. Example of shortening the INT pulse by
Fig 23. AF timing diagram . . . . . . . . . . . . . . . . . . . . . . . .41
Fig 24. STOP bit functional diagram . . . . . . . . . . . . . . . .44
Fig 25. STOP bit release timing . . . . . . . . . . . . . . . . . . . .44
Fig 26. Interface selection . . . . . . . . . . . . . . . . . . . . . . . .45
Fig 27. SDI, SDO configurations . . . . . . . . . . . . . . . . . . .46
Fig 28. Data transfer overview . . . . . . . . . . . . . . . . . . . . .46
Fig 29. SPI-bus write example . . . . . . . . . . . . . . . . . . . . .47
Fig 30. SPI-bus read example . . . . . . . . . . . . . . . . . . . . .47
Fig 31. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Fig 32. Definition of START and STOP conditions. . . . . .48
Fig 33. System configuration . . . . . . . . . . . . . . . . . . . . . .49
Fig 34. Acknowledgement on the I
Fig 35. Bus protocol, writing to registers . . . . . . . . . . . . .50
Fig 36. Bus protocol, reading from registers . . . . . . . . . .50
Fig 37. Device diode protection diagram of PCF2129AT.51
Fig 38. I
Fig 39. I
Fig 40. I
Fig 41. Typical characteristic of frequency with respect
Fig 42. SPI-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Fig 43. I
PCF2129AT
Product data sheet
Block diagram of PCF2129AT . . . . . . . . . . . . . . . .3
Pin configuration for PCF2129AT (SO20) . . . . . . .4
Handling address registers . . . . . . . . . . . . . . . . . .5
Battery switch-over behavior in standard mode
with bit BIE set logic 1 (enabled) . . . . . . . . . . . . .15
Battery switch-over behavior in direct switching
mode with bit BIE set logic 1 (enabled) . . . . . . . .16
Battery switch-over circuit, simplified block
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Typical driving capability of V
with respect to the output load current I
Battery low detection behavior with bit BLIE
set logic 1 (enabled) . . . . . . . . . . . . . . . . . . . . . .19
Power failure event due to battery discharge:
reset occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
valid for both I
interrupt when timed out . . . . . . . . . . . . . . . . . . .32
the TS pin (for example, for tamper detection) . .34
logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
clearing the MSF flag . . . . . . . . . . . . . . . . . . . . . .40
to temperature . . . . . . . . . . . . . . . . . . . . . . . . . . .57
OL
DD
DD
2
C-bus timing diagram; rise and fall times
on pin SDA/CE . . . . . . . . . . . . . . . . . . . . . . . .55
as a function of temperature . . . . . . . . . . . . .55
as a function of V
2
C-bus and SPI-bus . . . . . . . . . . .22
DD
. . . . . . . . . . . . . . . . . . . .56
2
C-bus . . . . . . . . . . . .49
BBS
: (V
All information provided in this document is subject to legal disclaimers.
BBS
BBS
- V
Rev. 5 — 12 February 2013
DD
. . . . .18
)
Fig 44. Package outline SOT163-1 (SO20) . . . . . . . . . . 62
Fig 45. Tape and reel details for PCF2129AT . . . . . . . . . 63
Fig 46. Footprint information for reflow soldering of
refer to 30 % and 70 % . . . . . . . . . . . . . . . . . . . . 61
SO20 package . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Integrated RTC, TCXO and quartz crystal
PCF2129AT
© NXP B.V. 2013. All rights reserved.
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