C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 157
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C8051F960-A-GQ
Manufacturer Part Number
C8051F960-A-GQ
Description
8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F960-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
128 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F960-A-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F960-A-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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SFR Definition 11.8. DMA0NBAH: Memory Base Address High Byte
SFR Page = 0x2; SFR Address = 0xCB
SFR Definition 11.9. DMA0NBAL: Memory Base Address Low Byte
SFR Page = 0x2; SFR Address = 0xCA
Note: This sfr is a DMA channel indirect register. Select the desired channel first using the DMA0SEL sfr.
Note: This sfr is a DMA channel indirect register. Select the desired channel first using the DMA0SEL sfr.
7:4
3:0
7:0
Bit
Bit
Name
Reset
Name
Reset
Type
Type
Bit
Bit
NBAH[3:0]
NBAL[7:0]
Unused
Name
Name
R
7
0
7
0
R
6
0
6
0
Read = 0b, Write = Don’t Care
Memory Base Address High Byte.
Sets high byte of the memory base address which is the DMA0 XRAM start-
ing address of the selected channel if the channel’s address offset
DMA0NAO is reset to 0.
Memory Base Address Low Byte.
Sets low byte of the memory base address which is the DMA0 XRAM start-
ing address of the selected channel if the channel’s address offset
DMA0NAO is reset to 0.
R
5
0
5
0
Rev. 0.5
R
4
0
4
0
NBAH[7:0]
R/W
Function
Function
3
0
3
0
2
0
2
0
NBAH[3:0]
R/W
C8051F96x
1
0
1
0
0
0
0
0
157
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