C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 186
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C8051F960-A-GQ
Manufacturer Part Number
C8051F960-A-GQ
Description
8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F960-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
128 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Available stocks
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Manufacturer
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Company:
Part Number:
C8051F960-A-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F960-A-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
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C8051F96x
14.4.1. AES Block Cipher Encryption using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power con-
sumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use with the code examples. The steps are documented in the datasheet for complete-
ness.
Steps to encrypt data using Simple AES block encryption (ECB mode)
186
Prepare encryption Key and data to be encrypted in xram.
Reset AES module by clearing bit 2 of AES0BCFG.
Disable the first three DMA channels by clearing bits 0 to 2 in the DMA0EN sfr.
Configure the first DMA channel for the AES0KIN sfr
Configure the second DMA channel for the AES0BIN sfr.
Configure the third DMA channel for the AES0YOUT sfr
Clear first three DMA interrupts by clearing bits 0 to 2 in the DMA0INT sfr.
Enable first three DMA channels setting bits 0 to 2 in the DMA0EN sfr
Configure the AES Module data flow for AES Block Cipher by writing 0x00 to the AES0DCFG sfr.
Write key size to bits 1 and 0 of the AES0BCFG
Configure the AES core for encryption by setting the bit 2 of AES0BCFG
Initiate the encryption operation be setting bit 3 of AES0BCFG
Wait on the DMA interrupt from DMA channel 2
Disable the AES Module by clearing bit 2 of AES0BCFG
Disable the DMA by writing 0x00 to DMA0EN
Select the first DMA channel by writing 0x00 to the DMA0SEL sfr
Configure the second DMA channel to move xram to AES0KIN sfr by writing 0x05 to the DMA0NCF sfr
Write 0x01 tDMA0NMD to enable wrapping
Write the xram location of encryption key to the DMA0NBAH and DMA0NBAL sfrs.
Write the key length in bytes to the DMA0NSZL sfr
Clear the DMA0NSZH sfr
Clear the DMA0NAOH and DMA0NAOL sfrs.
Select the second DMA channel by writing 0x01 to the DMA0SEL sfr.
Configure the second DMA channel to move xram to the AES0BIN sfr by writing 0x06 to the DMA0NCF sfr.
Clear DMA0NMD to disable wrapping.
Write the xram address of the data to be encrypted to the DMA0NBAH and DMA0NBAL sfrs.
Write the number of bytes to be encrypted in multiples of 16 bytes to the DMA0NSZH and DMA0NSZL sfrs.
Clear the DMA0NAOH and DMA0NAOL sfrs.
Select the third DMA channel by writing 0x02 to the DMA0SEL sfr
Configure the third DMA channel to move the contents of the AES0YOUT sfr to xram by writing 0x08 to the
DMA0NCF sfr.
Enable transfer complete interrupt by setting bit 7 of DMA0NCF sfr.
Clear DMA0NMD to disable wrapping.
Write the xram address for encrypted data to the DMA0NBAH and DMA0NBAL sfrs.
Write the number of bytes to be encrypted in multiples of 16 bytes to the DMA0NSZH and DMA0NSZL sfrs.
Clear the DMA0NAOH and DMA0NAOL sfrs.
Rev. 0.5
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